From WikiChip
Difference between revisions of "amd/ryzen 7/1700"
< amd‎ | ryzen 7

Line 80: Line 80:
 
| package module 1    = {{packages/amd/socket am4}}
 
| package module 1    = {{packages/amd/socket am4}}
 
}}
 
}}
'''Ryzen 7 1700''' is a {{arch|64}} [[octa-core]] high-end performance [[x86]] desktop microprocessor introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1700 operates at a base frequency of 3 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of 3.7 GHz. This MPU supports up to 64 GIB of dual-channel non-ECC DDR4-2400 memory.
+
'''Ryzen 7 1700''' is a {{arch|64}} [[octa-core]] high-end performance [[x86]] desktop microprocessor introduced by [[AMD]] in early [[2017]]. This processor is based on AMD's {{amd|Zen|Zen microarchitecture|l=arch}} and is fabricated on a [[14 nm process]]. The 1700 operates at a base frequency of 3 GHz with a [[TDP]] of 65 W and a {{amd|Precision Boost|Boost}} frequency of 3.7 GHz. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory.
  
 
== Cache ==
 
== Cache ==

Revision as of 17:27, 2 March 2017

Template:mpu Ryzen 7 1700 is a 64-bit octa-core high-end performance x86 desktop microprocessor introduced by AMD in early 2017. This processor is based on AMD's Zen microarchitecture and is fabricated on a 14 nm process. The 1700 operates at a base frequency of 3 GHz with a TDP of 65 W and a Boost frequency of 3.7 GHz. This MPU supports up to 64 GiB of dual-channel non-ECC DDR4-2400 memory.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back

L3$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  4x8 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCNo
Max Mem64 GiB
Controllers1
Channels2
Max Bandwidth35.76 GiB/s
36,618.24 MiB/s
38.397 GB/s
38,397.008 MB/s
0.0349 TiB/s
0.0384 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes20
Configs1x16+1x4, 2x8+1x4, 1x8+3x4


Graphics

This processor has no integrated graphics.

Features

Shop

<amazon type="simple-listing1" search-title="AMD Ryzen 7 1700" search-phrase="AMD Ryzen 7 1700" />

Die Shot

See also: Zen § Die Shot
  • 14 nm process
  • 12 metal layers
  • 2,000 meters of signals
  • 4,800,000,000 transistors
  • ~195 mm²

amd zen octa-core die shot.png

Facts about "Ryzen 7 1700 - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Ryzen 7 1700 - AMD#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supportfalse +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 + and Advanced Encryption Standard Instruction Set Extension +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max pcie lanes20 +
supported memory typeDDR4-2400 +