From WikiChip
Difference between revisions of "cavium/octeon plus/cn5750-600bg1217-sp"
< cavium‎ | octeon plus

Line 90: Line 90:
 
}}
 
}}
 
'''CN5750-600 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.
 
'''CN5750-600 SP''' is a {{arch|64}} [[dodeca-core]] [[MIPS]] storage processor (SP) designed by [[Cavium]] and introduced in [[2007]]. This processor, which incorporates twelve {{cavium|cnMIPS|l=arch}} cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as [[RAID]], networking, TCP & [[QoS]] acceleration.
 +
 +
== Cache ==
 +
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 +
{{cache size
 +
|l1 cache=576 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1d cache=192 KiB
 +
|l1d break=12x16 KiB
 +
|l2 cache=2 MiB
 +
|l2 break=1x2 MiB
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR2-800
 +
|ecc=Yes
 +
|max mem=
 +
|controllers=1
 +
|channels=2
 +
|width=64 bit
 +
|max bandwidth=11.92 GiB/s
 +
|bandwidth schan=5.96 GiB/s
 +
|bandwidth dchan=11.92 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
|pcie revision=1.0
 +
|pcie lanes=8
 +
|pcie config=x4
 +
|pcie config 2=x8
 +
|uart=yes
 +
|gp io=Yes
 +
}}
 +
 +
== Networking ==
 +
Interface options:
 +
* 8-lanes [[PCIe]] + 8-lanes PCIe
 +
* 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
 +
* 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]
 +
{{network
 +
|mii opts=Yes
 +
|sgmii=yes
 +
|sgmii ports=4
 +
|xaui=1
 +
|xaui ports=1
 +
}}
 +
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|compression=Yes
 +
|decompression=Yes
 +
|tcp=Yes
 +
|qos=Yes
 +
|raid=Yes
 +
|raid5=Yes
 +
|raid6=Yes
 +
}}
 +
 +
== Block diagram ==
 +
[[File:cn57xx block diagram.png|750px]]
 +
 +
== Datasheet ==
 +
* [[:File:CN57XX PB Rev 1.2.pdf|OCTEON CN57XX Processors Product Brief]]

Revision as of 13:31, 29 December 2016

Template:mpu CN5750-600 SP is a 64-bit dodeca-core MIPS storage processor (SP) designed by Cavium and introduced in 2007. This processor, which incorporates twelve cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 dual channel ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance of storage and network software such as RAID, networking, TCP & QoS acceleration.

Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$576 KiB
589,824 B
0.563 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB  
L1D$192 KiB
196,608 B
0.188 MiB
12x16 KiB  
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB  

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-800
Supports ECCYes
Controllers1
Channels2
Width64 bit
Max Bandwidth11.92 GiB/s
12,206.08 MiB/s
12.799 GB/s
12,799.003 MB/s
0.0116 TiB/s
0.0128 TB/s
Bandwidth
Single 5.96 GiB/s
Double 11.92 GiB/s

Expansions

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision1.0
Max Lanes8
Configsx4, x8
UART
GP I/OYes


Networking

Interface options:

  • 8-lanes PCIe + 8-lanes PCIe
  • 8-lanes PCIe + 4 lanes PCIe + 4x [SGMII OR XAUI]
  • 2x [4-lanes PCIe] + 2x [4x SGMII OR XAUI]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
XAUIYes (Ports: 1)
SGMIIYes (Ports: 4)

Hardware Accelerators

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Networking
TCPYes
QoSYes
Compression
CompressionYes
DecompressionYes
RAID
RAID 5Yes
RAID 6Yes

Block diagram

cn57xx block diagram.png

Datasheet

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5750-600bg1217-sp&oldid=32367"
Facts about "CN5750-600 SP - Cavium"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5750-600 SP - Cavium#io +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
has hardware raid 5 supporttrue +
has hardware raid 6 supporttrue +
l1$ size576 KiB (589,824 B, 0.563 MiB) +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels2 +
max pcie lanes8 +
supported memory typeDDR2-800 +