From WikiChip
Difference between revisions of "cavium/octeon plus/cn5830-600bg1521-nsp"
Line 39: | Line 39: | ||
| core model = | | core model = | ||
| core stepping = | | core stepping = | ||
− | | process = | + | | process = 90 nm |
| transistors = | | transistors = | ||
| technology = CMOS | | technology = CMOS |
Revision as of 18:29, 27 December 2016
Template:mpu CN5830-600 NSP is a 64-bit quad-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2007. This processor, which incorporates four cnMIPS cores, operates at 600 MHz and supports up to DDR2-800 ECC memory. This MPU includes a number of hardware accelerators specifically for improving the performance network services software such as encryption, RegEx, compression/decompression, and TCP acceleration.
Contents
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
|||||||||||||||||||||||||
|
Memory controller
Integrated Memory Controller
|
||||||||||||||
|
Expansions
Expansion Options
|
||||||||||||||||
|
Networking
Networking
|
||||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
Hardware Accelerators
|
||||||||||||||||||||||||
|
Block diagram
Datasheet
Facts about "CN5830-600 NSP - Cavium"