From WikiChip
Difference between revisions of "cavium/octeon plus/cn5850-900bg1521-nsp"
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| socket 0 = BGA-1521 | | socket 0 = BGA-1521 | ||
| socket 0 type = BGA | | socket 0 type = BGA | ||
+ | }} | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=576 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=64-way set associative | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=12x16 KiB | ||
+ | |l1d desc=64-way set associative | ||
+ | |l2 cache=2 MiB | ||
+ | |l2 break=1x2 MiB | ||
+ | |l2 desc=8-way set associative | ||
}} | }} |
Revision as of 02:26, 15 December 2016
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "CN5850-900 NSP - Cavium"
l1$ size | 576 KiB (589,824 B, 0.563 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |