From WikiChip
Difference between revisions of "cavium/octeon plus/cn5830-800bg1521-scp"
< cavium‎ | octeon plus

Line 101: Line 101:
 
|l1d break=4x16 KiB
 
|l1d break=4x16 KiB
 
|l1d desc=64-way set associative
 
|l1d desc=64-way set associative
−
|l2 cache=1 MiB
+
|l2 cache=2 MiB
 
|l2 break=1x2 MiB
 
|l2 break=1x2 MiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
}}
 
}}

Revision as of 01:22, 15 December 2016

Template:mpu


Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB64-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
4x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5830-800bg1521-scp&oldid=31937"
Facts about "CN5830-800 SCP - Cavium"
RDF feed
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +