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Difference between revisions of "cavium/octeon plus/cn5830-1000bg1521-exp"
< cavium‎ | octeon plus

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|l1d break=4x16 KiB
 
|l1d break=4x16 KiB
 
|l1d desc=64-way set associative
 
|l1d desc=64-way set associative
−
|l2 cache=1 MiB
+
|l2 cache=2 MiB
 
|l2 break=1x2 MiB
 
|l2 break=1x2 MiB
 
|l2 desc=8-way set associative
 
|l2 desc=8-way set associative
 
}}
 
}}

Revision as of 02:22, 15 December 2016

Template:mpu


Cache

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB64-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
4x16 KiB64-way set associative 
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  1x2 MiB8-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon_plus/cn5830-1000bg1521-exp&oldid=31935"
Facts about "CN5830-1000 EXP - Cavium"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN5830-1000 EXP - Cavium#package +
base frequency1,000 MHz (1 GHz, 1,000,000 kHz) +
core count4 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5830-1000bg1521-exp +
has ecc memory supporttrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5830-1000 EXP +
nameCavium CN5830-1000 EXP +
packageFCBGA-1521 +
part numberCN5830-1000BG1521-EXP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +