Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon/cn3860-400bg1521-scp"
(Created page with "{{cavium title|CN3860-400 SCP}} {{mpu | name = Cavium CN3860-400 SCP | no image = | image = octeon cn38xx.png | image size =...") |
|||
| Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| + | The '''CN3860-400 SCP''' is a {{arch|64}} [[hexadeca-core]] [[MIPS]] secure network communication [[microprocessor]] (SNP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates sixteen {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | ||
Revision as of 20:42, 10 December 2016
Template:mpu The CN3860-400 SCP is a 64-bit hexadeca-core MIPS secure network communication microprocessor (SNP) designed by Cavium and introduced in 2005. This processor, which incorporates sixteen cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and encryption. This MPU supports up to 16 GiB of DDR2-800 ECC memory.