From WikiChip
Difference between revisions of "cavium/octeon/cn3630-400bg1521-exp"
Line 52: | Line 52: | ||
| max memory addr = | | max memory addr = | ||
− | | electrical = | + | | electrical = Yes |
− | | power = | + | | power = 14 W |
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
− | The '''CN3630-400 EXP''' is a {{arch|64}} [[quad-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. | + | The '''CN3630-400 EXP''' is a {{arch|64}} [[quad-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz and dissipates 14 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. |
== Cache == | == Cache == |
Revision as of 13:52, 10 December 2016
Template:mpu The CN3630-400 EXP is a 64-bit quad-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates four cnMIPS cores, operates at 400 MHz and dissipates 14 Watts. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||
|
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||||||
|
Expansions
![]() |
Expansion Options
|
|||||||||||||||
|
Networking
![]() |
Networking
|
|||||||
|
Hardware Accelerators
[Edit/Modify Accelerators Info]
![]() |
Hardware Accelerators
|
|||||||||||||||||
|
Block diagram
Datasheet
Facts about "CN3630-400 EXP - Cavium"
has ecc memory support | true + |
has hardware accelerators for data compression | true + |
has hardware accelerators for data decompression | true + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for regular expression | true + |
has hardware accelerators for tcp packet processing | true + |
l1$ size | 160 KiB (163,840 B, 0.156 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l1i$ description | 64-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + |
max memory bandwidth | 5.96 GiB/s (6,103.04 MiB/s, 6.4 GB/s, 6,399.501 MB/s, 0.00582 TiB/s, 0.0064 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-800 + |