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Difference between revisions of "cavium/octeon/cn3110-300bg868-nsp"
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The '''CN3110-300 NSP''' is a {{arch|64}} [[single-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 3 Watts. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | The '''CN3110-300 NSP''' is a {{arch|64}} [[single-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 300 MHz and dissipates 3 Watts. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. |
Revision as of 17:23, 9 December 2016
Template:mpu The CN3110-300 NSP is a 64-bit single-core MIPS network service microprocessor (NSP) designed by Cavium and introduced in 2006. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 3 Watts. This processor includes a number of hardware accelerators for network services such as encryption, compression & decompression, RegEx engine, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
Integrated Memory Controller
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Expansions
Expansion Options
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Networking
Networking
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Features
Hardware acceleration units:
- Encryption
- Regular Expression
- Compression/Decompression (e.g. GZIP)
- QoS
- TCP Acceleration
Block diagram
Datasheet
Facts about "CN3110-300 NSP - Cavium"
has ecc memory support | true + |
l1$ size | 40 KiB (40,960 B, 0.0391 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-667 + |