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Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
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|l2 desc=8-way set associative | |l2 desc=8-way set associative | ||
}} | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR2-667 | ||
+ | |ecc=Yes | ||
+ | |max mem=4 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=64 bit | ||
+ | |max bandwidth=4.97 GiB/s | ||
+ | |bandwidth schan=4.97 GiB/s | ||
+ | }} | ||
+ | |||
+ | Optional low-latency controller for content-based processing and meta data | ||
+ | |||
+ | {{memory controller | ||
+ | |type=DDR2-667 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 GiB | ||
+ | |controllers=1 | ||
+ | |channels=1 | ||
+ | |width=16 bit | ||
+ | |max bandwidth=1.24 GiB/s | ||
+ | |bandwidth schan=1.24 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |pcix width=32 bit | ||
+ | |pcix clock=100 MHz | ||
+ | |pcix rate=381.5 MiB/s | ||
+ | |pci extra=host or slave | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |usb rate=60 MB/s | ||
+ | |usb extra=host / PHY | ||
+ | |uart=yes | ||
+ | |uart ports=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | {{network | ||
+ | |mii opts=Yes | ||
+ | |rgmii=yes | ||
+ | |rgmii ports=3 | ||
+ | |gmii=yes | ||
+ | |gmii ports=1 | ||
+ | |pcm=Yes | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | Hardware acceleration units: | ||
+ | * [[Encryption]] | ||
+ | ** [[DES]], [[3DES]], [[AES]] (up to 256 bit), [[SHA1]], [[SHA-2]] upto [[SHA-512]], [[RSA]], DH | ||
+ | * QoS | ||
+ | * TCP Acceleration | ||
+ | |||
+ | == Block diagram == | ||
+ | [[File:octeon cn31xx block diagram.png|750px]] | ||
+ | |||
+ | == Datasheet == | ||
+ | * [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]] |
Revision as of 15:55, 9 December 2016
Template:mpu The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
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Networking
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Features
Hardware acceleration units:
Block diagram
Datasheet
Facts about "CN3120-550 SCP - Cavium"
has ecc memory support | true + |
l1$ size | 80 KiB (81,920 B, 0.0781 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
max memory bandwidth | 4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-667 + |