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Difference between revisions of "cavium/octeon/cn3005-500bg350-cp"
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− | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. | + | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. |
== Cache == | == Cache == | ||
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{{memory controller | {{memory controller | ||
|type=DDR2-533 | |type=DDR2-533 | ||
− | |ecc= | + | |ecc=Yes |
|max mem=2 GiB | |max mem=2 GiB | ||
|controllers=1 | |controllers=1 | ||
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|bandwidth schan=1,017 MiB/s | |bandwidth schan=1,017 MiB/s | ||
}} | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions | ||
+ | |usb revision=2.0 | ||
+ | |usb ports=1 | ||
+ | |uart=2 | ||
+ | |gp io=Yes | ||
+ | }} | ||
+ | |||
+ | == Networking == | ||
+ | * 1x RGMII/MII | ||
+ | * 1x GMII/MII | ||
+ | * 32-bit, 66 MHz PCI host or slave | ||
+ | * TDM/PCM interface for glueless VoIP support | ||
+ | |||
+ | == Features == | ||
+ | Hardware acceleration units: | ||
+ | * Hardware implementation for common security algorithms: | ||
+ | ** DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH | ||
+ | * QoS | ||
+ | * TCP Acceleration |
Revision as of 07:50, 8 December 2016
Template:mpu The CN3005-500 CP is a 64-bit single-core MIPS communication microprocessor (CP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory.
Cache
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Networking
- 1x RGMII/MII
- 1x GMII/MII
- 32-bit, 66 MHz PCI host or slave
- TDM/PCM interface for glueless VoIP support
Features
Hardware acceleration units:
- Hardware implementation for common security algorithms:
- DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH
- QoS
- TCP Acceleration
Facts about "CN3005-500 CP - Cavium"
has ecc memory support | false + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 2-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
max memory channels | 1 + |
supported memory type | DDR2-533 + |