Semiconductor & Computer Engineering
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Difference between revisions of "cavium/octeon/cn3005-500bg350-scp"
| Line 14: | Line 14: | ||
| part number 3 = | | part number 3 = | ||
| market = Embedded | | market = Embedded | ||
| − | | first announced = | + | | first announced = January 30, 2006 |
| − | | first launched = | + | | first launched = May 1, 2006 |
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
| Line 52: | Line 52: | ||
| max memory addr = | | max memory addr = | ||
| − | | electrical = | + | | electrical = Yes |
| − | | power = | + | | power = 4 W |
| v core = | | v core = | ||
| v core tolerance = | | v core tolerance = | ||
| Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| − | The '''CN3005-500 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[ | + | The '''CN3005-500 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. |
Revision as of 04:41, 8 December 2016
Template:mpu The CN3005-500 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in early 2006. This processor, which incorporates a single cnMIPS core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.