From WikiChip
Difference between revisions of "cavium/octeon/cn3005-300bg350-scp"
< cavium‎ | octeon

(Created page with "{{cavium title|CN3005-300 SCP}} {{mpu | name = Cavium CN3005-300 SCP | no image = cn3005-15.png | image = | image size = | c...")
 
Line 52: Line 52:
 
| max memory addr    =  
 
| max memory addr    =  
  
−
| electrical          =  
+
| electrical          = Yes
−
| power              =  
+
| power              = 2 W
 
| v core              =  
 
| v core              =  
 
| v core tolerance    =  
 
| v core tolerance    =  

Revision as of 05:36, 8 December 2016

Template:mpu The CN3005-300 SCP is a 64-bit single-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2005. This processor, which incorporates a single cnMIPS core, operates at 300 MHz and dissipates 2 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3005-300bg350-scp&oldid=30604"