Semiconductor & Computer Engineering
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Difference between revisions of "cavium/microarchitectures/cnmips"
(Created page with "{{cavium title|cnMIPS|arch}} '''cnMIPS''' or '''cnMIPS64''' is a microarchitecture implementing the {{mips|MIPS64}} ISA designed by Cavium for their {{cavium|Octeon}}...") |
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{{cavium title|cnMIPS|arch}} | {{cavium title|cnMIPS|arch}} | ||
| − | '''cnMIPS''' or '''cnMIPS64''' is | + | {{microarchitecture |
| + | | name = cnMIPS | ||
| + | | designer = Cavium | ||
| + | | manufacturer = TSMC | ||
| + | | introduction = | ||
| + | | phase-out = | ||
| + | | process = | ||
| + | | cores = 2 | ||
| + | | cores 2 = 4 | ||
| + | | cores 3 = 8 | ||
| + | | cores 4 = 16 | ||
| + | |||
| + | | pipeline = Yes | ||
| + | | type = Superscalar | ||
| + | | type 2 = | ||
| + | | type N = | ||
| + | | OoOE = <!-- Yes or No only --> | ||
| + | | speculative = <!-- Yes or No only --> | ||
| + | | renaming = <!-- Yes or No only --> | ||
| + | | stages = 5 | ||
| + | | issues = 2 | ||
| + | |||
| + | | inst = Yes | ||
| + | | isa = MIPS64 | ||
| + | | feature = | ||
| + | | extension = | ||
| + | | extension 2 = | ||
| + | |||
| + | | cache = <!-- yes for cache info --> | ||
| + | | l1i = | ||
| + | | l1i per = | ||
| + | | l1i desc = | ||
| + | | l1d = | ||
| + | | l1d per = | ||
| + | | l1d desc = | ||
| + | | l2 = | ||
| + | | l2 per = | ||
| + | | l2 desc = | ||
| + | | l3 = | ||
| + | | l3 per = | ||
| + | | l3 desc = | ||
| + | |||
| + | | core names = <!-- Yes if specify --> | ||
| + | | core name = | ||
| + | | core name 2 = | ||
| + | | core name N = | ||
| + | |||
| + | | succession = <!-- yes for succession info --> | ||
| + | | predecessor = | ||
| + | | predecessor link = | ||
| + | | successor = | ||
| + | | successor link = | ||
| + | | successor 2 = | ||
| + | | successor 2 link = | ||
| + | | successor N = | ||
| + | | successor N link = | ||
| + | }} | ||
| + | '''cnMIPS''' or '''cnMIPS64''' is the first [[microarchitecture]] implementing the {{mips|MIPS64}} ISA designed by [[Cavium]] for their {{cavium|Octeon}} family of processors. The "cn" stands for "Cavium Networks" or "content networking". | ||
| + | |||
| + | == History == | ||
| + | The cnMIPS was [[Cavium]]'s first [[microarchitecture]] developed completely in-house from the ground up. The cnMIPS is also the first implementation of the {{mips|MIPS64|MIPS64 Release 2}} ISA. The design was done by a group of 35 engineers who previously worked on [[DEC]]'s {{decc|EV7}} based in [[wikipedia:Marlboro, Massachusetts|Marlboro, Massachusetts]] under the lead of Cavium's CTO Richard Kessler (who was previously the chief architect of the {{decc|EV7}}). The fully custom final design proved to be around three to five times faster than the synthesized MIPS64 core. | ||
Revision as of 22:39, 6 December 2016
| Edit Values | |
| cnMIPS µarch | |
| General Info |
cnMIPS or cnMIPS64 is the first microarchitecture implementing the MIPS64 ISA designed by Cavium for their Octeon family of processors. The "cn" stands for "Cavium Networks" or "content networking".
History
The cnMIPS was Cavium's first microarchitecture developed completely in-house from the ground up. The cnMIPS is also the first implementation of the MIPS64 Release 2 ISA. The design was done by a group of 35 engineers who previously worked on DEC's EV7 based in Marlboro, Massachusetts under the lead of Cavium's CTO Richard Kessler (who was previously the chief architect of the EV7). The fully custom final design proved to be around three to five times faster than the synthesized MIPS64 core.