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Difference between revisions of "amd/k5/amd-k5-pr120abr"
< amd‎ | k5

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== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}}
 
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}}
 
 
{{cache info
 
{{cache info
|l1i cache=16 KB
+
|l1i cache=16 KiB
|l1i break=1x16 KB
+
|l1i break=1x16 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=8 KB
+
|l1d cache=8 KiB
|l1d break=1x8 KB
+
|l1d break=1x8 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
 
|l1d extra=
 
|l1d extra=

Revision as of 00:16, 21 September 2016

Template:mpu AMD-K5-PR120ABR was a 32-bit x86 microprocessor developed by AMD and released in late 1996. This chip was sold as Pentium 120 MHz equivalent. The processor used AMD's 5k86 version of their K5 microarchitecture, operating at 90 MHz with a TDP of 12.6 W.

Cache

Main article: K5 § Cache
Cache Info [Edit Values]
L1I$ 16 KiB
16,384 B
0.0156 MiB
1x16 KiB 4-way set associative
L1D$ 8 KiB
8,192 B
0.00781 MiB
1x8 KiB 4-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

  • P120 P-Rating
  • Auto-power down state
  • Stop clock state

See also

Facts about "AMD-K5-PR120ABR - AMD"
l1d$ description4-way set associative +
l1i$ description4-way set associative +
processor p-ratingP120 +