Semiconductor & Computer Engineering
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Difference between revisions of "amd/k5/amd-k5-pr75abr"
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== Cache == | == Cache == | ||
{{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | {{main|amd/microarchitectures/k5#Memory_Hierarchy|l1=K5 § Cache}} | ||
| − | |||
{{cache info | {{cache info | ||
| − | |l1i cache=16 | + | |l1i cache=16 KiB |
| − | |l1i break=1x16 | + | |l1i break=1x16 KiB |
|l1i desc=4-way set associative | |l1i desc=4-way set associative | ||
|l1i extra= | |l1i extra= | ||
| − | |l1d cache=8 | + | |l1d cache=8 KiB |
| − | |l1d break=1x8 | + | |l1d break=1x8 KiB |
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
|l1d extra= | |l1d extra= | ||
| Line 96: | Line 95: | ||
|l3 extra= | |l3 extra= | ||
}} | }} | ||
| + | |||
== Die Shot == | == Die Shot == | ||
[[File:AMD K5 PR75 die.JPG|650px]] | [[File:AMD K5 PR75 die.JPG|650px]] | ||
Revision as of 23:14, 20 September 2016
Template:mpu AMD-K5-PR75ABR was a 32-bit x86 microprocessor developed by AMD and released in 1996. This chip was sold as Pentium 75 MHz equivalent. The processor used AMD's 2nd revision of their K5 microarchitecture, operating at 75 MHz with a TDP of 11.8 W.
Contents
Cache
- Main article: K5 § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 16 KiB 16,384 B 0.0156 MiB |
1x16 KiB 4-way set associative |
| L1D$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative |
Die Shot
Graphics
This SoC has no integrated graphics processing unit.
Features
- P75 P-Rating
- Auto-power down state
- Stop clock state
See also
Facts about "AMD-K5-PR75ABR - AMD"
| l1d$ description | 4-way set associative + |
| l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
| l1i$ description | 4-way set associative + |
| l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
| processor p-rating | P75 + |