Semiconductor & Computer Engineering
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Difference between revisions of "intel/xeon e3/e3-1270 v5"
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1i cache=128 | + | |l1i cache=128 KiB |
| − | |l1i break=4x32 | + | |l1i break=4x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
|l1i extra=(per core, write-back) | |l1i extra=(per core, write-back) | ||
| − | |l1d cache=128 | + | |l1d cache=128 KiB |
| − | |l1d break=4x32 | + | |l1d break=4x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d extra=(per core, write-back) | |l1d extra=(per core, write-back) | ||
| − | |l2 cache=1 | + | |l2 cache=1 MiB |
| − | |l2 break=4x256 | + | |l2 break=4x256 KiB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
|l2 extra=(per core) | |l2 extra=(per core) | ||
| Line 92: | Line 92: | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
}} | }} | ||
| + | |||
== Graphics == | == Graphics == | ||
This chip has no integrated graphics processing unit. | This chip has no integrated graphics processing unit. | ||
Revision as of 23:12, 20 September 2016
Template:mpu The Xeon E3-1270 V5 is an entry-level workstations and servers 64-bit x86 quad-core microprocessor introduced by Intel in October 2015. This Skylake-based chip operates at 3.6 GHz with turbo boost of 4 GHz. The E3-1270 V5 has a TDP of 80 Watts and supports up to 64 GB of dual-channel DDR3/4. This MPU has no integrated graphics processor.
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L1D$ | 128 KiB 131,072 B 0.125 MiB |
4x32 KiB 8-way set associative (per core, write-back) |
| L2$ | 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB |
4x256 KiB 4-way set associative (per core) |
| L3$ | 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB |
4x2 MiB |
Graphics
This chip has no integrated graphics processing unit.
Memory controller
| Integrated Memory Controller | |
| Type | DDR3L-1333, DDR3L-1600, DDR3L-RS1333, DDR3L-RS1600, DDR4-1866, DDR4-2133, DDR4-RS1866, DDR4-RS2133 |
| Controllers | 1 |
| Channels | 2 |
| ECC Support | Yes |
| Max bandwidth | 34.1 GB/s |
| Max memory | 64 GB |
Expansions
Features
Facts about "Xeon E3-1270 v5 - Intel"
| l1d$ description | 8-way set associative + |
| l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
| l2$ description | 4-way set associative + |
| l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
| l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |