Semiconductor & Computer Engineering
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Difference between revisions of "amd/am286zx-lx/ng286lx-12"
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{{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | ||
{{cache info | {{cache info | ||
| − | |l1 cache=0 | + | |l1 cache=0 KiB |
| − | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= | ||
| − | |l2 cache=0 | + | |l2 cache=0 KiB |
| − | |l2 break=1x0 | + | |l2 break=1x0 KiB |
}} | }} | ||
Revision as of 22:05, 20 September 2016
Template:mpu NG286LX-12 was a 16-bit system on chip designed by AMD and introduced in late 1990. This chip, which incorporated the N80C286-12 core operating at 12 MHz integrated with all the other components typically found on an IBM PC AT motherboard (e.g. Interrupt Controller, Clock Generator, Bus Controller, and DMA Controller). This model is an enhanced version of the NG286ZX-12 which added a few more power saving features.
Contents
Cache
- Main article: 80286 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
| L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics
This chip had no integrated graphics processing unit.
Features
- Protected mode
- on-die bus controller
- on-die clock generator
- on-die DMA controller
- on-die interrupt controller
- Direct link to a FPU coprocessor (Am287)
- Direct link to a Keyboard controller
- CPU shutdown mode; System shutdown mode
- Staggered DRAM refresh; slow-refresh DRAM support