From WikiChip
Difference between revisions of "amd/am286/n80c286-12"
(→Cache) |
|||
Line 79: | Line 79: | ||
{{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | {{main|intel/microarchitectures/80286#Memory_Hierarchy|l1=80286 § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1 cache=0 | + | |l1 cache=0 KiB |
− | |l1 break=1x0 | + | |l1 break=1x0 KiB |
|l1 desc= | |l1 desc= | ||
|l1 extra= | |l1 extra= | ||
− | |l2 cache=0 | + | |l2 cache=0 KiB |
− | |l2 break=1x0 | + | |l2 break=1x0 KiB |
}} | }} | ||
Revision as of 21:53, 20 September 2016
Template:mpu N80C286-12 was a member of AMD's Am286 family specifically designed for embedded applications, likely battery-powered. These chips were remade by AMD in static CMOS design (as opposed to nMOS), resulting in considerably lower power dissipation. This MPU was rated to operate at 12 MHz and was packaged in a 68-pin Plastic Leadless Chip Carrier package.
Contents
Cache
- Main article: 80286 § Cache
Cache Info [Edit Values] | ||
L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics
This chip had no integrated graphics processing unit.
Features
- Protected mode
- Supports FPU coprocessor (Am287)
Documents
- AMD 80C286 Datasheet (December 1991), Publication #11625