Semiconductor & Computer Engineering
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Difference between revisions of "amd/k6-2/k6-2-300afr"
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File:AMD K6-2 300 AFR CPU.jpg|Week 42, 1998 | File:AMD K6-2 300 AFR CPU.jpg|Week 42, 1998 | ||
File:AMD-K6-2 300AFR processor.JPG|Week 51, 1998 | File:AMD-K6-2 300AFR processor.JPG|Week 51, 1998 | ||
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Revision as of 23:22, 3 August 2016
Template:mpu K6-2/300AFR was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB of 100 MHz consumed 17.2 W. Note that K6-2/300AFR-66 is an identical model with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead.
Cache
- Main article: K6-2 § Cache
L2$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L2$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
| L1D$ | 32 KB "KB" is not declared as a valid unit of measurement for this property. |
1x32 KB 2-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Auto-power down state
- Stop clock state
Gallery
Week 42, 1998
Week 51, 1998
Documents
DataSheet
- AMD-K6-2 Processor Data Sheet; Publication #21850 Revision J/0, February 2000
Facts about "K6-2/300AFR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |