From WikiChip
Difference between revisions of "amd/k6-2/k6-2-300afr-66"
< amd‎ | k6-2

Line 80: Line 80:
 
}}
 
}}
 
'''K6-2/300AFR-66''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1998]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 300 MHz with a [[FSB]] of 66 MHz consumed 17.2 W. Note that this is an identical model to {{\\|k6-2-300afr|K6-2/300AFR}} with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead of 100 MHz.
 
'''K6-2/300AFR-66''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1998]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 300 MHz with a [[FSB]] of 66 MHz consumed 17.2 W. Note that this is an identical model to {{\\|k6-2-300afr|K6-2/300AFR}} with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead of 100 MHz.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}}
 +
[[L2$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
 +
{{cache info
 +
|l1i cache=32 KB
 +
|l1i break=1x32 KB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=32 KB
 +
|l1d break=1x32 KB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=
 +
|l2 break=
 +
|l2 desc=
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}
 +
 +
== Graphics ==
 +
This SoC has no integrated graphics processing unit.
 +
 +
== Features ==
 +
{{mpu features
 +
| mmx  = true
 +
| 3dnow = true
 +
}}
 +
* Auto-power down state
 +
* Stop clock state

Revision as of 22:41, 3 August 2016

Template:mpu K6-2/300AFR-66 was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1998 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB of 66 MHz consumed 17.2 W. Note that this is an identical model to K6-2/300AFR with a multiplier of 4.5 instead of 3 designed to support a 66 MHz bus instead of 100 MHz.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
 		1x32 KB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/k6-2/k6-2-300afr-66&oldid=23242"
Facts about "K6-2/300AFR-66 - AMD"
RDF feed
l1d$ description2-way set associative +
l1i$ description2-way set associative +