Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "intel/core i3/i3-6100u"
| Line 1: | Line 1: | ||
{{intel title|Core i3-6100U}} | {{intel title|Core i3-6100U}} | ||
{{mpu | {{mpu | ||
| − | | name = | + | | name = Intel Core i3-6100U |
| no image = Yes | | no image = Yes | ||
| image = | | image = | ||
Revision as of 03:08, 13 May 2016
Template:mpu Core i3-6100U is a 64-bit dual-core low-end mobile microprocessor introduced by Intel late 2015. This processor, which is based on the Skylake microarchitecture and manufactured in 14 nm process, has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the HD Graphics 520 GPU clocked at 300 MHz with a max frequency of 1 GHz.
Cache
- Main article: Skylake § Cache
| Cache Info [Edit Values] | ||
| L1I$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L1D$ | 64 KB "KB" is not declared as a valid unit of measurement for this property. |
2x32 KB 8-way set associative (per core, write-back) |
| L2$ | 512 KB "KB" is not declared as a valid unit of measurement for this property. |
2x256 KB 4-way set associative (per core, write-back) |
| L3$ | 3 MB "MB" is not declared as a valid unit of measurement for this property. |
shared |
Facts about "Core i3-6100U - Intel"
| l1d$ description | 8-way set associative + |
| l1i$ description | 8-way set associative + |
| l2$ description | 4-way set associative + |
| l3$ description | shared + |