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Difference between revisions of "intel/core i3/i3-6100u"
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'''Core i3-6100U''' is a {{arch|64}} [[dual-core]] low-end mobile [[microprocessor]] introduced by [[Intel]] late 2015. This processor, which is based on the {{intel|Skylake}} microarchitecture and manufactured in [[14 nm process]], has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the {{intel|HD Graphics 520}} [[GPU]] clocked at 300 MHz with a max frequency of 1 GHz.
 
'''Core i3-6100U''' is a {{arch|64}} [[dual-core]] low-end mobile [[microprocessor]] introduced by [[Intel]] late 2015. This processor, which is based on the {{intel|Skylake}} microarchitecture and manufactured in [[14 nm process]], has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the {{intel|HD Graphics 520}} [[GPU]] clocked at 300 MHz with a max frequency of 1 GHz.
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== Cache ==
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{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
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{{cache info
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|l1i cache=64 KB
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|l1i break=2x32 KB
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|l1i desc=8-way set associative
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|l1i extra=(per core, write-back)
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|l1d cache=64 KB
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|l1d break=2x32 KB
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|l1d desc=8-way set associative
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|l1d extra=(per core, write-back)
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|l2 cache=512 KB
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|l2 break=2x256 KB
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|l2 desc=4-way set associative
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|l2 extra=(per core, write-back)
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|l3 cache=3 MB
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|l3 desc=shared
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}}

Revision as of 03:06, 13 May 2016

Template:mpu Core i3-6100U is a 64-bit dual-core low-end mobile microprocessor introduced by Intel late 2015. This processor, which is based on the Skylake microarchitecture and manufactured in 14 nm process, has a base frequency of 2.3 GHz with a TDP of 15 W with a configurable TDP-down of 7.5 W operating at 800 MHz. This processor incorporates the HD Graphics 520 GPU clocked at 300 MHz with a max frequency of 1 GHz.

Cache

Main article: Skylake § Cache
Cache Info [Edit Values]
L1I$ 64 KB
"KB" is not declared as a valid unit of measurement for this property.
2x32 KB 8-way set associative (per core, write-back)
L1D$ 64 KB
"KB" is not declared as a valid unit of measurement for this property.
2x32 KB 8-way set associative (per core, write-back)
L2$ 512 KB
"KB" is not declared as a valid unit of measurement for this property.
2x256 KB 4-way set associative (per core, write-back)
L3$ 3 MB
"MB" is not declared as a valid unit of measurement for this property.
shared
Facts about "Core i3-6100U - Intel"
l1d$ description8-way set associative +
l1i$ description8-way set associative +
l2$ description4-way set associative +
l3$ descriptionshared +