From WikiChip
Difference between revisions of "Template:10 nm comp header"

(Created page with "{| class="wikitable" style="float:left; margin:0; margin-right:-1px; font-family: monospace;" |- ! colspan="2" |   |- ! style="text-align: right;" colspan="2" | Proce...")
 
(fixed)
 
(3 intermediate revisions by one other user not shown)
Line 6: Line 6:
 
  |-
 
  |-
 
  ! style="text-align: right;" colspan="2" | 1st Production
 
  ! style="text-align: right;" colspan="2" | 1st Production
 +
|-
 +
! style="text-align: center;" rowspan="3" | Litho-<br>graphy || style="text-align: right;" | Lithography
 +
|-
 +
! style="text-align: right;" | Immersion
 +
|-
 +
! style="text-align: right;" | Exposure
 
  |-
 
  |-
 
  ! style="text-align: center;" rowspan="2" | Wafer || style="text-align: right;" | Type
 
  ! style="text-align: center;" rowspan="2" | Wafer || style="text-align: right;" | Type
Line 11: Line 17:
 
  ! style="text-align: right;" | Size
 
  ! style="text-align: right;" | Size
 
  |-
 
  |-
−
  ! style="text-align: center;" rowspan="2" | Transistor || style="text-align: right;" | Type
+
  ! style="text-align: center;" rowspan="2" | Tran-<br>sistor || style="text-align: right;" | Type
 
  |-
 
  |-
 
  ! style="text-align: right;" | Voltage
 
  ! style="text-align: right;" | Voltage
Line 23: Line 29:
 
  ! style="text-align: right;" | Height
 
  ! style="text-align: right;" | Height
 
  |-
 
  |-
−
  ! style="text-align: right;" colspan="2" | Gate Pitch (L<sub>g</sub>)
+
  ! style="text-align: right;" colspan="2" | Gate Length (L<sub>g</sub>)
 
  |-
 
  |-
 
  ! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP)
 
  ! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP)
 
  |-
 
  |-
−
  ! style="text-align: right;" colspan="2" | Interconnect Pitch (M1P)
+
  ! style="text-align: right;" colspan="2" | Minimum Metal Pitch (MMP)
 
  |-
 
  |-
−
  ! style="text-align: right;" rowspan="3" | SRAM bitcell || style="text-align: right;" | High-Perf (HP)
+
  ! style="text-align: right;" rowspan="3" | SRAM <br>bitcell || style="text-align: right;" | High-Perf (HP)
 
  |-
 
  |-
 
  ! style="text-align: right;" | High-Density (HD)
 
  ! style="text-align: right;" | High-Density (HD)
Line 35: Line 41:
 
  ! style="text-align: right;" | Low-Voltage (LV)
 
  ! style="text-align: right;" | Low-Voltage (LV)
 
  |-
 
  |-
−
  ! style="text-align: right;" rowspan="3" | DRAM bitcell || style="text-align: right;" | eDRAM
+
  ! style="text-align: right;" rowspan="3" | DRAM <br>bitcell || style="text-align: right;" | eDRAM
 
|}
 
|}

Latest revision as of 18:09, 19 March 2025

 
Process Name
1st Production
Litho-
graphy 		Lithography
Immersion
Exposure
Wafer Type
Size
Tran-
sistor 		Type
Voltage
 
Fin Pitch
Width
Height
Gate Length (Lg)
Contacted Gate Pitch (CPP)
Minimum Metal Pitch (MMP)
SRAM
bitcell 		High-Perf (HP)
High-Density (HD)
Low-Voltage (LV)
DRAM
bitcell 		eDRAM
Retrieved from "https://en.wikichip.org/w/index.php?title=Template:10_nm_comp_header&oldid=103021"