Semiconductor & Computer Engineering
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Difference between revisions of "Template:planar comp header"
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| − | {| class="wikitable" style="float:left; margin:0; margin-right:-1px; font-family: monospace;" | + | {| class="wikitable" style="float:left; margin:0; margin-right:-1px; font-family: monospace; width: 25%;" |
|- | |- | ||
! colspan="2" | | ! colspan="2" | | ||
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! style="text-align: right;" colspan="2" | 1st Production | ! style="text-align: right;" colspan="2" | 1st Production | ||
|- | |- | ||
| − | ! style="text-align: center;" rowspan="3" | | + | ! style="text-align: center;" rowspan="3" | Litho-<br>graphy || style="text-align: right;" | Lithography |
|- | |- | ||
! style="text-align: right;" | Immersion | ! style="text-align: right;" | Immersion | ||
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! style="text-align: right;" | Size | ! style="text-align: right;" | Size | ||
|- | |- | ||
| − | ! style="text-align: center;" rowspan="2" | | + | ! style="text-align: center;" rowspan="2" | Tran-<br>sistor || style="text-align: right;" | Type |
|- | |- | ||
! style="text-align: right;" | Voltage | ! style="text-align: right;" | Voltage | ||
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! style="text-align: right;" colspan="2" | | ! style="text-align: right;" colspan="2" | | ||
|- | |- | ||
| − | ! style="text-align: right;" colspan="2" | Gate | + | ! style="text-align: right;" colspan="2" | Gate Length (L<sub>g</sub>) |
|- | |- | ||
! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ! style="text-align: right;" colspan="2" | Contacted Gate Pitch (CPP) | ||
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! style="text-align: right;" colspan="2" | Minimum Metal Pitch (MMP) | ! style="text-align: right;" colspan="2" | Minimum Metal Pitch (MMP) | ||
|- | |- | ||
| − | ! style="text-align: right;" rowspan="3" | SRAM bitcell || style="text-align: right;" | High-Perf (HP) | + | ! style="text-align: right;" rowspan="3" | SRAM <br>bitcell || style="text-align: right;" | High-Perf (HP) |
|- | |- | ||
! style="text-align: right;" | High-Density (HD) | ! style="text-align: right;" | High-Density (HD) | ||
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! style="text-align: right;" | Low-Voltage (LV) | ! style="text-align: right;" | Low-Voltage (LV) | ||
|- | |- | ||
| − | ! style="text-align: right;" rowspan="3" | DRAM bitcell || style="text-align: right;" | eDRAM | + | ! style="text-align: right;" rowspan="3" | DRAM <br>bitcell || style="text-align: right;" | eDRAM |
|} | |} | ||
Latest revision as of 16:36, 19 March 2025
| Process Name | |
|---|---|
| 1st Production | |
| Litho- graphy |
Lithography |
| Immersion | |
| Exposure | |
| Wafer | Type |
| Size | |
| Tran- sistor |
Type |
| Voltage | |
| Metal Layers | |
| Gate Length (Lg) | |
| Contacted Gate Pitch (CPP) | |
| Minimum Metal Pitch (MMP) | |
| SRAM bitcell |
High-Perf (HP) |
| High-Density (HD) | |
| Low-Voltage (LV) | |
| DRAM bitcell |
eDRAM |