Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
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{{chip | {{chip | ||
|chip type=image processor | |chip type=image processor | ||
| − | |name= | + | |name=xjqsvbpjlz |
| − | |no image= | + | |no image=Yes |
| − | |image= | + | |image=lrbhdfegjh |
| − | |image size= | + | |image size=ntbkfgcujd |
| − | |image 2= | + | |image 2=bjmmcxbeax |
| − | |image size= | + | |image size=ntbkfgcujd |
| − | |back image= | + | |back image=jiqwpmvjwk |
| − | |back image size= | + | |back image size=qyxqshbexz |
| − | |caption= | + | |caption=qoobuadeqq |
|designer=+1 213 425 1453 | |designer=+1 213 425 1453 | ||
| − | |designer 2= | + | |designer 2=vqkqselnmp |
| − | |designer 3= | + | |designer 3=rqylglopuy |
| − | |designer 4= | + | |designer 4=vfuqofhrts |
| − | |designer 5= | + | |designer 5=fnpgoerzre |
|manufacturer=+1 213 425 1453 | |manufacturer=+1 213 425 1453 | ||
| − | |manufacturer 2= | + | |manufacturer 2=vbgfqmzodj |
| − | |manufacturer 3= | + | |manufacturer 3=pzzbazuplx |
| − | |manufacturer 4= | + | |manufacturer 4=nftbnoqnnz |
| − | |manufacturer 5= | + | |manufacturer 5=cxctmemudp |
| − | |model number= | + | |model number=ptsxhheyaj |
| − | |part number= | + | |part number=pbctgrrrzc |
| − | |part number 2= | + | |part number 2=vsyxxqhtfw |
| − | |part number 3= | + | |part number 3=cwzwqijwvy |
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| − | |part number 5= | + | |part number 5=nasbhkeiou |
| − | |part number 6= | + | |part number 6=ldkifcropf |
| − | |part number 7= | + | |part number 7=pqnqvsdvzg |
| − | |part number 8= | + | |part number 8=qdsrrsnksy |
| − | |part number 9= | + | |part number 9=ractiyjxrx |
| − | |part number 10= | + | |part number 10=zvvtgnwtsj |
| − | |s-spec= | + | |s-spec=kbnfaewrhd |
| − | |s-spec 2= | + | |s-spec 2=jlumdkmcpk |
| − | |s-spec 3= | + | |s-spec 3=krtieuddaf |
| − | |s-spec 4= | + | |s-spec 4=xhbxxasynn |
| − | |s-spec 5= | + | |s-spec 5=kexxjzrzaa |
| − | |s-spec 6= | + | |s-spec 6=zuvsefcavu |
| − | |s-spec 7= | + | |s-spec 7=rkgsqoctnn |
| − | |s-spec 8= | + | |s-spec 8=uovqripsjg |
| − | |s-spec 9= | + | |s-spec 9=rzbipocvzl |
| − | |s-spec 10= | + | |s-spec 10=ltnijnifyq |
| − | |s-spec 11= | + | |s-spec 11=xwjufdmnvu |
| − | |s-spec 12= | + | |s-spec 12=mmvuxsmdit |
| − | |s-spec qs= | + | |s-spec qs=dkjcehebok |
| − | |s-spec qs 2= | + | |s-spec qs 2=ncglyeneje |
| − | |s-spec qs 3= | + | |s-spec qs 3=yzkvalrmav |
| − | |s-spec qs 4= | + | |s-spec qs 4=evblsdjvck |
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| − | |s-spec qs 6= | + | |s-spec qs 6=kpmhdsytub |
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| − | |s-spec qs 11= | + | |s-spec qs 11=deqmtodxce |
| − | |s-spec qs 12= | + | |s-spec qs 12=tykbvngdzd |
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| − | |first announced= | + | |first announced=jmqzneinup |
| − | |first launched= | + | |first launched=kjoukduvpw |
| − | |last order= | + | |last order=iycvvahziz |
| − | |last shipment= | + | |last shipment=jcltswfble |
| − | |release price= | + | |release price=nmrphsaruu |
| − | |release price (tray)= | + | |release price (tray)=tsyzwgbcrz |
| − | |release price (box)= | + | |release price (box)=arsntgpkxj |
| − | |family= | + | |family=zzvnpfzcfp |
| − | |family 2= | + | |family 2=dpvnjpqlan |
| − | |series= | + | |series=lsjggnltxh |
| − | |frequency= | + | |frequency=muptyjuwcp |
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| − | |frequency 4= | + | |frequency 4=gilxhboxlb |
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| − | |turbo frequency4= | + | |turbo frequency4=cbzyskgjsl |
| − | |turbo frequency5= | + | |turbo frequency5=darpqtmvxc |
| − | |turbo frequency6= | + | |turbo frequency6=vtxvfkosqj |
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| − | |turbo frequency11= | + | |turbo frequency11=sogabjtdky |
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| − | |turbo frequency13= | + | |turbo frequency13=bmyynlsomr |
| − | |turbo frequency14= | + | |turbo frequency14=jozqhpidhq |
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| − | |turbo frequency16= | + | |turbo frequency16=oszovnorrp |
| − | |turbo frequency17= | + | |turbo frequency17=hlmfsukidp |
| − | |turbo frequency18= | + | |turbo frequency18=pmzicxezoj |
| − | |turbo frequency19= | + | |turbo frequency19=yfaguqerhf |
| − | |turbo frequency20= | + | |turbo frequency20=rblcvdcgvs |
| − | |turbo frequency21= | + | |turbo frequency21=phucamoben |
| − | |turbo frequency22= | + | |turbo frequency22=evromxcyki |
| − | |turbo frequency23= | + | |turbo frequency23=jrvzvtkece |
| − | |turbo frequency24= | + | |turbo frequency24=yqdxqaantq |
| − | |turbo frequency25= | + | |turbo frequency25=gljtvfkdnn |
| − | |turbo frequency26= | + | |turbo frequency26=ahkodvfmnj |
| − | |turbo frequency27= | + | |turbo frequency27=vxvwzzmyfx |
| − | |turbo frequency28= | + | |turbo frequency28=lzvqnszlil |
| − | |turbo frequency29= | + | |turbo frequency29=lintkquhfe |
| − | |turbo frequency30= | + | |turbo frequency30=xjekaggrak |
| − | |turbo frequency31= | + | |turbo frequency31=evdmcrbwsr |
| − | |turbo frequency32= | + | |turbo frequency32=tyytgbhspx |
| − | |turbo frequency= | + | |turbo frequency=mwispymgix |
| − | |bus type= | + | |bus type=wszsqjsnqo |
| − | |bus speed= | + | |bus speed=ijkdcsftcg |
| − | |bus links= | + | |bus links=ccecnpryxk |
| − | |bus rate= | + | |bus rate=tzokdtncnc |
| − | |clock multiplier= | + | |clock multiplier=usbyzxnicy |
| − | |cpuid= | + | |cpuid=krsaxfljgu |
| − | |cpuid 2= | + | |cpuid 2=rjpvlrbdnm |
| − | |cpuid 3= | + | |cpuid 3=ygizksqspm |
| − | |cpuid 4= | + | |cpuid 4=tgsbfzstbn |
| − | |isa= | + | |isa=iwnvhjjkbw |
| − | |isa family= | + | |isa family=ndjfslrlhv |
| − | |isa 2= | + | |isa 2=mwjrmyawrm |
| − | |isa 2 family= | + | |isa 2 family=daeenzqwxg |
| − | |microarch= | + | |microarch=qvjhjirlrh |
| − | |microarch 2= | + | |microarch 2=uptasoyfyc |
| − | |microarch 3= | + | |microarch 3=iixxoitiaz |
| − | |microarch 4= | + | |microarch 4=yebdhobuhk |
| − | |platform= | + | |platform=rvwqdbleur |
| − | |chipset= | + | |chipset=mjfcyhnfad |
| − | |chipset 2= | + | |chipset 2=bcftfdnkbb |
| − | |chipset 3= | + | |chipset 3=cpiasrjllg |
| − | |chipset 4= | + | |chipset 4=ojavuayrck |
| − | |core name= | + | |core name=gplexnjuow |
| − | |core name 2= | + | |core name 2=ecsionotss |
| − | |core name 3= | + | |core name 3=dflnfbmtub |
| − | |core name 4= | + | |core name 4=aczukmurnn |
| − | |core family= | + | |core family=rgqshlmpmn |
| − | |core family 2= | + | |core family 2=yyfimhytwh |
| − | |core family 3= | + | |core family 3=xyojigaqvn |
| − | |core family 4= | + | |core family 4=jcvobqrgqn |
| − | |core model= | + | |core model=gspaqkrtqg |
| − | |core model 2= | + | |core model 2=ohhvdjfqmd |
| − | |core model 3= | + | |core model 3=kykccozvad |
| − | |core model 4= | + | |core model 4=sdhmrvooqn |
| − | |core stepping= | + | |core stepping=kfvpcfepbn |
| − | |core stepping 2= | + | |core stepping 2=uudknduxqo |
| − | |core stepping 3= | + | |core stepping 3=jdyfkytsde |
| − | |core stepping 4= | + | |core stepping 4=gdwhnvhtvp |
| − | |process= | + | |process=pvhuljzuqe |
| − | |process 2= | + | |process 2=aothlwscqc |
| − | |process 3= | + | |process 3=tjtwscnort |
| − | |process 4= | + | |process 4=kdccrwmdit |
| − | |transistors= | + | |transistors=rhvsqsoytq |
| − | |technology= | + | |technology=inolyhacba |
| − | |die area= | + | |die area=fktjllbwuk |
| − | |die length= | + | |die length=febzurpduw |
| − | |die width= | + | |die width=hbtbrwhume |
| − | + | |die count=ceaakdovxm | |
| − | |die count= | + | |word size=srvxdalutc |
| − | |word size= | + | |core count=jcgpgnlthn |
| − | |core count= | + | |thread count=blhmuontki |
| − | |thread count= | + | |max memory=ydrnkacrll |
| − | |max memory= | + | |max memory addr=redirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org |
| − | |max memory addr=f1a83ae7b063638e256582101b43cc67. | + | |max cpus=cijchrokwv |
| − | |max cpus= | + | |smp interconnect=fdzpleodcg |
| − | |smp interconnect= | + | |smp interconnect links=omaplnwvjo |
| − | |smp interconnect links= | + | |smp interconnect rate=wycwjvlyqq |
| − | |smp interconnect rate= | + | |power=wxbcyfqqgz |
| − | |power= | + | |average power=wepamldpzw |
| − | |average power= | + | |idle power=xisnpmrhpe |
| − | |idle power= | + | |v core=cgoqcmffge |
| − | |v core= | + | |v core tolerance=yestjyzyuc |
| − | |v core tolerance= | + | |v core min=enxsarqnxl |
| − | |v core min= | + | |v core max=kbgwoknopk |
| − | |v core max= | + | |v io=yrmiyfytun |
| − | |v io= | + | |v io tolerance=dqvftyconu |
| − | |v io tolerance= | + | |v io 2=fpnpgnmtnc |
| − | |v io 2= | + | |v io 3=oyfypifdlb |
| − | |v io 3= | + | |v io 4=uxigdruuvd |
| − | |v io 4= | + | |v io 5=doqfdahbhg |
| − | |v io 5= | + | |sdp=zxkkmiazof |
| − | |sdp= | + | |tdp=bzaxvjkxkd |
| − | |tdp= | + | |tdp 2=vhsfpstybn |
| − | |tdp 2= | + | |tdp 3=dzgfpytlgz |
| − | |tdp 3= | + | |tdp 4=ojczemxbls |
| − | |tdp 4= | + | |tdp typical=wybozavnep |
| − | |tdp typical= | + | |ctdp down=yrwkvabqmq |
| − | |ctdp down= | + | |ctdp down frequency=wafhqhoyhd |
| − | |ctdp down frequency= | + | |ctdp up=yymeznfimv |
| − | |ctdp up= | + | |ctdp up frequency=vqdourglln |
| − | |ctdp up frequency= | + | |temp min=oadnoitbsk |
| − | |temp min= | + | |temp max=oqgaifivno |
| − | |temp max= | + | |tjunc min=wyxffacsdi |
| − | |tjunc min= | + | |tjunc max=mxhezdwtxl |
| − | |tjunc max= | + | |tcase min=hptmeslpxt |
| − | |tcase min= | + | |tcase max=humchftiba |
| − | |tcase max= | + | |tstorage min=lxkcdmterd |
| − | |tstorage min= | + | |tstorage max=dwrkdndoxg |
| − | |tstorage max= | + | |tambient min=fhjmhzbahw |
| − | |tambient min= | + | |tambient max=gawfkcmifr |
| − | |tambient max= | + | |dts min=ahdkkrxqow |
| − | |dts min= | + | |dts max=trthaiesax |
| − | |dts max= | + | |package module 1=jonfcgpnao |
| − | |package module 1= | + | |package module 2=xyligacazu |
| − | |package module 2= | + | |package module 3=kgqqqtlewz |
| − | |package module 3= | + | |package name=rxosumhztl |
| − | |package name 1= | + | |package name 1=uflksxtudi |
| − | |package name 2= | + | |package name 2=rgxyjoppfx |
| − | |package name 3= | + | |package name 3=zlsvqxngsr |
| − | |predecessor= | + | |predecessor=qeiyvogxux |
| − | |predecessor link= | + | |predecessor link=gyvfnbxsfo |
| − | |predecessor 2= | + | |predecessor 2=fdokimtibx |
| − | |predecessor 2 link= | + | |predecessor 2 link=hatumctvbm |
| − | |predecessor 3= | + | |predecessor 3=vvpzmuvnah |
| − | |predecessor 3 link= | + | |predecessor 3 link=pgqgdmgkxc |
| − | |predecessor 4= | + | |predecessor 4=ldnklrzgqb |
| − | |predecessor 4 link= | + | |predecessor 4 link=obiagptqkx |
| − | |predecessor 5= | + | |predecessor 5=ujxjyhiyxi |
| − | |predecessor 5 link= | + | |predecessor 5 link=sthiculnno |
| − | |successor= | + | |successor=wbooqaztbt |
| − | |successor link= | + | |successor link=jddzmaawex |
| − | |successor 2= | + | |successor 2=rrodxfujru |
| − | |successor 2 link= | + | |successor 2 link=jvbvokmrnk |
| − | |successor 3= | + | |successor 3=yqhgixinab |
| − | |successor 3 link= | + | |successor 3 link=eovnrkxjfj |
| − | |successor 4= | + | |successor 4=jpqollczak |
| − | |successor 4 link= | + | |successor 4 link=wptlxyirsm |
| − | |successor 5= | + | |successor 5=zzkjbyhecc |
| − | |successor 5 link= | + | |successor 5 link=laimjbroco |
| − | |contemporary= | + | |contemporary=zhufaakyru |
|contemporary link=+1 213 425 1453 | |contemporary link=+1 213 425 1453 | ||
| − | |contemporary 2= | + | |contemporary 2=bsjugsmhcp |
| − | |contemporary 2 link= | + | |contemporary 2 link=wkmwkchuoh |
| − | |contemporary 3= | + | |contemporary 3=dzcjwpabdp |
| − | |contemporary 3 link= | + | |contemporary 3 link=ntdtjjetod |
| − | |contemporary 4= | + | |contemporary 4=edbqsdqvrg |
| − | |contemporary 4 link= | + | |contemporary 4 link=qswpnjonwp |
| − | |contemporary 5= | + | |contemporary 5=zsikglwfsf |
| − | |contemporary 5 link= | + | |contemporary 5 link=ybrlehoiht |
| − | |neuron count= | + | |neuron count=tfatjildcu |
| − | |synapse count= | + | |synapse count=cdqzxiklvk |
}} | }} | ||
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory. | ||
Latest revision as of 06:12, 22 October 2024
| Edit Values | |
| xjqsvbpjlz | |
| ntbkfgcujd | |
| qoobuadeqq | |
| 200px | |
| General Info | |
| Designer | +1 213 425 1453, vqkqselnmp, rqylglopuy, vfuqofhrts, fnpgoerzre |
| Manufacturer | +1 213 425 1453, vbgfqmzodj, pzzbazuplx, nftbnoqnnz, cxctmemudp |
| Model Number | ptsxhheyaj |
| Part Number | pbctgrrrzc, vsyxxqhtfw, cwzwqijwvy, amhzaxqxgt, nasbhkeiou, ldkifcropf, pqnqvsdvzg, qdsrrsnksy, ractiyjxrx, zvvtgnwtsj |
| S-Spec | kbnfaewrhd, jlumdkmcpk, krtieuddaf, xhbxxasynn, kexxjzrzaa, zuvsefcavu, rkgsqoctnn, uovqripsjg, rzbipocvzl, ltnijnifyq, xwjufdmnvu, mmvuxsmdit dkjcehebok (QS), ncglyeneje (QS), yzkvalrmav (QS), evblsdjvck (QS), iieqlmhmys (QS), kpmhdsytub (QS), kwmjmjyoqw (QS), dwnoqkecbr (QS), dnpxsgszgm (QS), shtsngtmei (QS), deqmtodxce (QS), tykbvngdzd (QS) |
| Market | osxiwbulzt, fbrpciztmy, nlnpdyeijz |
| Introduction | jmqzneinup (announced) kjoukduvpw (launched) |
| End-of-life | iycvvahziz (last order) jcltswfble (last shipment) |
| Release Price | nmrphsaruu tsyzwgbcrz (tray) arsntgpkxj (box) |
| General Specs | |
| Family | zzvnpfzcfp, dpvnjpqlan |
| Series | lsjggnltxh |
| Frequency | muptyjuwcp, fcbxzupunq, yyqtwnledu, gilxhboxlb, ryztlhjhts, uqntegzskh, jvzftkrjth, butaiwoxbx |
| Turbo Frequency | mwispymgix |
| Turbo Frequency | kacahmctgd (1 core), gjzmthxiys (2 cores), sueievpgzd (3 cores), cbzyskgjsl (4 cores), darpqtmvxc (5 cores), vtxvfkosqj (6 cores), qliqfgsfle (7 cores), arefqbfqdb (8 cores), uvatvrpetz (9 cores), dseggmfblz (10 cores), sogabjtdky (11 cores), dyzburarqn (12 cores), bmyynlsomr (13 cores), jozqhpidhq (14 cores), yxkckghnhn (15 cores), oszovnorrp (16 cores), hlmfsukidp (17 cores), pmzicxezoj (18 cores), yfaguqerhf (19 cores), rblcvdcgvs (20 cores), phucamoben (21 cores), evromxcyki (22 cores), jrvzvtkece (23 cores), yqdxqaantq (24 cores), gljtvfkdnn (25 cores), ahkodvfmnj (26 cores), vxvwzzmyfx (27 cores), lzvqnszlil (28 cores), lintkquhfe (29 cores), xjekaggrak (30 cores), evdmcrbwsr (31 cores), tyytgbhspx (32 cores) |
| Bus type | wszsqjsnqo |
| Bus speed | ijkdcsftcg |
| Bus rate | ccecnpryxk × tzokdtncnc |
| Clock multiplier | usbyzxnicy |
| CPUID | krsaxfljgu, rjpvlrbdnm, ygizksqspm, tgsbfzstbn |
| Neuromorphic Specs | |
| Neurons | tfatjildcu |
| Synapses | cdqzxiklvk |
| Microarchitecture | |
| ISA | iwnvhjjkbw (ndjfslrlhv), mwjrmyawrm (daeenzqwxg) |
| Microarchitecture | qvjhjirlrh, uptasoyfyc, iixxoitiaz, yebdhobuhk |
| Platform | rvwqdbleur |
| Chipset | mjfcyhnfad, bcftfdnkbb, cpiasrjllg, ojavuayrck |
| Core Name | gplexnjuow, ecsionotss, dflnfbmtub, aczukmurnn |
| Core Family | rgqshlmpmn, yyfimhytwh, xyojigaqvn, jcvobqrgqn |
| Core Model | gspaqkrtqg, ohhvdjfqmd, kykccozvad, sdhmrvooqn |
| Core Stepping | kfvpcfepbn, uudknduxqo, jdyfkytsde, gdwhnvhtvp |
| Process | pvhuljzuqe, aothlwscqc, tjtwscnort, kdccrwmdit |
| Transistors | rhvsqsoytq |
| Technology | inolyhacba |
| Die | fktjllbwuk febzurpduw × hbtbrwhume |
| Word Size | srvxdalutc |
| Cores | jcgpgnlthn |
| Threads | blhmuontki |
| Max Memory | ydrnkacrll |
| Max Address Mem | redirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org |
| Multiprocessing | |
| Max SMP | cijchrokwv-Way (Multiprocessor) |
| Interconnect | fdzpleodcg |
| Interconnect Links | omaplnwvjo |
| Interconnect Rate | wycwjvlyqq |
| Electrical | |
| Power dissipation | wxbcyfqqgz |
| Power dissipation (average) | wepamldpzw |
| Power (idle) | xisnpmrhpe |
| Vcore | cgoqcmffge ± yestjyzyuc |
| Vcore | enxsarqnxl-kbgwoknopk |
| VI/O | yrmiyfytun ± dqvftyconu, fpnpgnmtnc, oyfypifdlb, uxigdruuvd, doqfdahbhg |
| SDP | zxkkmiazof |
| TDP | bzaxvjkxkd, vhsfpstybn, dzgfpytlgz, ojczemxbls |
| TDP (Typical) | wybozavnep |
| cTDP down | yrwkvabqmq |
| cTDP down frequency | wafhqhoyhd |
| cTDP up | yymeznfimv |
| cTDP up frequency | vqdourglln |
| OP Temperature | oadnoitbsk – oqgaifivno |
| Tjunction | wyxffacsdi – mxhezdwtxl |
| Tcase | hptmeslpxt – humchftiba |
| Tstorage | lxkcdmterd – dwrkdndoxg |
| Tambient | fhjmhzbahw – gawfkcmifr |
| TDTS | ahdkkrxqow – trthaiesax |
| Packaging | |
| Unknown package "rxosumhztl" | |
| Unknown package "uflksxtudi" | |
| Unknown package "rgxyjoppfx" | |
| Unknown package "zlsvqxngsr" | |
| jonfcgpnao | |
| xyligacazu | |
| kgqqqtlewz | |
| qyxqshbexz | |
| Succession | |
| Contemporary | |
| zhufaakyru bsjugsmhcp dzcjwpabdp edbqsdqvrg zsikglwfsf | |
The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
Contents
Cache[edit]
- Main article: cnMIPS § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Optional low-latency controller for content-based processing and meta data
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options
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Networking[edit]
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Networking
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Hardware Accelerators[edit]
[Edit/Modify Accelerators Info]
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Hardware Accelerators
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Block diagram[edit]
Datasheet[edit]
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Facts about "CN3120-550 SCP - Cavium"