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Difference between revisions of "cavium/octeon/cn3120-550bg868-scp"
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{{cavium title|CN3120-550 SCP}}
 
{{cavium title|CN3120-550 SCP}}
−
{{mpu
+
{{chip
−
| name               = Cavium CN3120-550 SCP
+
|chip type=image processor
−
| no image           =  
+
|name=xjqsvbpjlz
−
| image               = octeon cn31xx.png
+
|no image=Yes
−
| image size         =  
+
|image=lrbhdfegjh
−
| caption             =  
+
|image size=ntbkfgcujd
−
| designer           = Cavium
+
|image 2=bjmmcxbeax
−
| manufacturer       = TSMC
+
|image size=ntbkfgcujd
−
| model number       = CN3120
+
|back image=jiqwpmvjwk
−
| part number         = CN3120-550BG868-SCP
+
|back image size=qyxqshbexz
−
| part number 1      =  
+
|caption=qoobuadeqq
−
| part number 2      =  
+
|designer=+1 213 425 1453
−
| part number 3       =  
+
|designer 2=vqkqselnmp
−
| market             = Embedded
+
|designer 3=rqylglopuy
−
| first announced     = January 30, 2006
+
|designer 4=vfuqofhrts
−
| first launched     = May 1, 2006
+
|designer 5=fnpgoerzre
−
| last order         =  
+
|manufacturer=+1 213 425 1453
−
| last shipment       =  
+
|manufacturer 2=vbgfqmzodj
−
| release price       =  
+
|manufacturer 3=pzzbazuplx
 +
|manufacturer 4=nftbnoqnnz
 +
|manufacturer 5=cxctmemudp
 +
|model number=ptsxhheyaj
 +
|part number=pbctgrrrzc
 +
|part number 2=vsyxxqhtfw
 +
|part number 3=cwzwqijwvy
 +
|part number 4=amhzaxqxgt
 +
|part number 5=nasbhkeiou
 +
|part number 6=ldkifcropf
 +
|part number 7=pqnqvsdvzg
 +
|part number 8=qdsrrsnksy
 +
|part number 9=ractiyjxrx
 +
|part number 10=zvvtgnwtsj
 +
|s-spec=kbnfaewrhd
 +
|s-spec 2=jlumdkmcpk
 +
|s-spec 3=krtieuddaf
 +
|s-spec 4=xhbxxasynn
 +
|s-spec 5=kexxjzrzaa
 +
|s-spec 6=zuvsefcavu
 +
|s-spec 7=rkgsqoctnn
 +
|s-spec 8=uovqripsjg
 +
|s-spec 9=rzbipocvzl
 +
|s-spec 10=ltnijnifyq
 +
|s-spec 11=xwjufdmnvu
 +
|s-spec 12=mmvuxsmdit
 +
|s-spec qs=dkjcehebok
 +
|s-spec qs 2=ncglyeneje
 +
|s-spec qs 3=yzkvalrmav
 +
|s-spec qs 4=evblsdjvck
 +
|s-spec qs 5=iieqlmhmys
 +
|s-spec qs 6=kpmhdsytub
 +
|s-spec qs 7=kwmjmjyoqw
 +
|s-spec qs 8=dwnoqkecbr
 +
|s-spec qs 9=dnpxsgszgm
 +
|s-spec qs 10=shtsngtmei
 +
|s-spec qs 11=deqmtodxce
 +
|s-spec qs 12=tykbvngdzd
 +
|market=osxiwbulzt
 +
|market 2=fbrpciztmy
 +
|market 3=nlnpdyeijz
 +
|first announced=jmqzneinup
 +
|first launched=kjoukduvpw
 +
|last order=iycvvahziz
 +
|last shipment=jcltswfble
 +
|release price=nmrphsaruu
 +
|release price (tray)=tsyzwgbcrz
 +
|release price (box)=arsntgpkxj
 +
|family=zzvnpfzcfp
 +
|family 2=dpvnjpqlan
 +
|series=lsjggnltxh
 +
|frequency=muptyjuwcp
 +
|frequency 2=fcbxzupunq
 +
|frequency 3=yyqtwnledu
 +
|frequency 4=gilxhboxlb
 +
|frequency 5=ryztlhjhts
 +
|frequency 6=uqntegzskh
 +
|frequency 7=jvzftkrjth
 +
|frequency 8=butaiwoxbx
 +
|turbo frequency1=kacahmctgd
 +
|turbo frequency2=gjzmthxiys
 +
|turbo frequency3=sueievpgzd
 +
|turbo frequency4=cbzyskgjsl
 +
|turbo frequency5=darpqtmvxc
 +
|turbo frequency6=vtxvfkosqj
 +
|turbo frequency7=qliqfgsfle
 +
|turbo frequency8=arefqbfqdb
 +
|turbo frequency9=uvatvrpetz
 +
|turbo frequency10=dseggmfblz
 +
|turbo frequency11=sogabjtdky
 +
|turbo frequency12=dyzburarqn
 +
|turbo frequency13=bmyynlsomr
 +
|turbo frequency14=jozqhpidhq
 +
|turbo frequency15=yxkckghnhn
 +
|turbo frequency16=oszovnorrp
 +
|turbo frequency17=hlmfsukidp
 +
|turbo frequency18=pmzicxezoj
 +
|turbo frequency19=yfaguqerhf
 +
|turbo frequency20=rblcvdcgvs
 +
|turbo frequency21=phucamoben
 +
|turbo frequency22=evromxcyki
 +
|turbo frequency23=jrvzvtkece
 +
|turbo frequency24=yqdxqaantq
 +
|turbo frequency25=gljtvfkdnn
 +
|turbo frequency26=ahkodvfmnj
 +
|turbo frequency27=vxvwzzmyfx
 +
|turbo frequency28=lzvqnszlil
 +
|turbo frequency29=lintkquhfe
 +
|turbo frequency30=xjekaggrak
 +
|turbo frequency31=evdmcrbwsr
 +
|turbo frequency32=tyytgbhspx
 +
|turbo frequency=mwispymgix
 +
|bus type=wszsqjsnqo
 +
|bus speed=ijkdcsftcg
 +
|bus links=ccecnpryxk
 +
|bus rate=tzokdtncnc
 +
|clock multiplier=usbyzxnicy
 +
|cpuid=krsaxfljgu
 +
|cpuid 2=rjpvlrbdnm
 +
|cpuid 3=ygizksqspm
 +
|cpuid 4=tgsbfzstbn
 +
|isa=iwnvhjjkbw
 +
|isa family=ndjfslrlhv
 +
|isa 2=mwjrmyawrm
 +
|isa 2 family=daeenzqwxg
 +
|microarch=qvjhjirlrh
 +
|microarch 2=uptasoyfyc
 +
|microarch 3=iixxoitiaz
 +
|microarch 4=yebdhobuhk
 +
|platform=rvwqdbleur
 +
|chipset=mjfcyhnfad
 +
|chipset 2=bcftfdnkbb
 +
|chipset 3=cpiasrjllg
 +
|chipset 4=ojavuayrck
 +
|core name=gplexnjuow
 +
|core name 2=ecsionotss
 +
|core name 3=dflnfbmtub
 +
|core name 4=aczukmurnn
 +
|core family=rgqshlmpmn
 +
|core family 2=yyfimhytwh
 +
|core family 3=xyojigaqvn
 +
|core family 4=jcvobqrgqn
 +
|core model=gspaqkrtqg
 +
|core model 2=ohhvdjfqmd
 +
|core model 3=kykccozvad
 +
|core model 4=sdhmrvooqn
 +
|core stepping=kfvpcfepbn
 +
|core stepping 2=uudknduxqo
 +
|core stepping 3=jdyfkytsde
 +
|core stepping 4=gdwhnvhtvp
 +
|process=pvhuljzuqe
 +
|process 2=aothlwscqc
 +
|process 3=tjtwscnort
 +
|process 4=kdccrwmdit
 +
|transistors=rhvsqsoytq
 +
|technology=inolyhacba
 +
|die area=fktjllbwuk
 +
|die length=febzurpduw
 +
|die width=hbtbrwhume
 +
|die count=ceaakdovxm
 +
|word size=srvxdalutc
 +
|core count=jcgpgnlthn
 +
|thread count=blhmuontki
 +
|max memory=ydrnkacrll
 +
|max memory addr=redirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org
 +
|max cpus=cijchrokwv
 +
|smp interconnect=fdzpleodcg
 +
|smp interconnect links=omaplnwvjo
 +
|smp interconnect rate=wycwjvlyqq
 +
|power=wxbcyfqqgz
 +
|average power=wepamldpzw
 +
|idle power=xisnpmrhpe
 +
|v core=cgoqcmffge
 +
|v core tolerance=yestjyzyuc
 +
|v core min=enxsarqnxl
 +
|v core max=kbgwoknopk
 +
|v io=yrmiyfytun
 +
|v io tolerance=dqvftyconu
 +
|v io 2=fpnpgnmtnc
 +
|v io 3=oyfypifdlb
 +
|v io 4=uxigdruuvd
 +
|v io 5=doqfdahbhg
 +
|sdp=zxkkmiazof
 +
|tdp=bzaxvjkxkd
 +
|tdp 2=vhsfpstybn
 +
|tdp 3=dzgfpytlgz
 +
|tdp 4=ojczemxbls
 +
|tdp typical=wybozavnep
 +
|ctdp down=yrwkvabqmq
 +
|ctdp down frequency=wafhqhoyhd
 +
|ctdp up=yymeznfimv
 +
|ctdp up frequency=vqdourglln
 +
|temp min=oadnoitbsk
 +
|temp max=oqgaifivno
 +
|tjunc min=wyxffacsdi
 +
|tjunc max=mxhezdwtxl
 +
|tcase min=hptmeslpxt
 +
|tcase max=humchftiba
 +
|tstorage min=lxkcdmterd
 +
|tstorage max=dwrkdndoxg
 +
|tambient min=fhjmhzbahw
 +
|tambient max=gawfkcmifr
 +
|dts min=ahdkkrxqow
 +
|dts max=trthaiesax
 +
|package module 1=jonfcgpnao
 +
|package module 2=xyligacazu
 +
|package module 3=kgqqqtlewz
 +
|package name=rxosumhztl
 +
|package name 1=uflksxtudi
 +
|package name 2=rgxyjoppfx
 +
|package name 3=zlsvqxngsr
 +
|predecessor=qeiyvogxux
 +
|predecessor link=gyvfnbxsfo
 +
|predecessor 2=fdokimtibx
 +
|predecessor 2 link=hatumctvbm
 +
|predecessor 3=vvpzmuvnah
 +
|predecessor 3 link=pgqgdmgkxc
 +
|predecessor 4=ldnklrzgqb
 +
|predecessor 4 link=obiagptqkx
 +
|predecessor 5=ujxjyhiyxi
 +
|predecessor 5 link=sthiculnno
 +
|successor=wbooqaztbt
 +
|successor link=jddzmaawex
 +
|successor 2=rrodxfujru
 +
|successor 2 link=jvbvokmrnk
 +
|successor 3=yqhgixinab
 +
|successor 3 link=eovnrkxjfj
 +
|successor 4=jpqollczak
 +
|successor 4 link=wptlxyirsm
 +
|successor 5=zzkjbyhecc
 +
|successor 5 link=laimjbroco
 +
|contemporary=zhufaakyru
 +
|contemporary link=+1 213 425 1453
 +
|contemporary 2=bsjugsmhcp
 +
|contemporary 2 link=wkmwkchuoh
 +
|contemporary 3=dzcjwpabdp
 +
|contemporary 3 link=ntdtjjetod
 +
|contemporary 4=edbqsdqvrg
 +
|contemporary 4 link=qswpnjonwp
 +
|contemporary 5=zsikglwfsf
 +
|contemporary 5 link=ybrlehoiht
 +
|neuron count=tfatjildcu
 +
|synapse count=cdqzxiklvk
 +
}}
 +
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
  
−
| family              = OCTEON
+
== Cache ==
−
| series              = CN3100
+
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
−
| locked              =  
+
{{cache size
−
| frequency          = 550 MHz
+
|l1 cache=80 KiB
−
| bus type            =  
+
|l1i cache=64 KiB
−
| bus speed          =  
+
|l1i break=2x32 KiB
−
| bus rate            =  
+
|l1i desc=4-way set associative
−
| bus links          =  
+
|l1d cache=16 KiB
−
| clock multiplier    =  
+
|l1d break=2x8 KiB
 +
|l1d desc=64-way set associative
 +
|l1d policy=Write-through
 +
|l2 cache=256 KiB
 +
|l2 break=1x128 KiB
 +
|l2 desc=8-way set associative
 +
}}
  
−
| isa family          = MIPS
+
== Memory controller ==
−
| isa                = MIPS64
+
{{memory controller
−
| microarch          = cnMIPS
+
|type=DDR2-667
−
| platform            =  
+
|ecc=Yes
−
| chipset            =
+
|max mem=4 GiB
−
| core name          = cnMIPS
+
|controllers=1
−
| core family        =  
+
|channels=1
−
| core model          =  
+
|width=64 bit
−
| core stepping      =  
+
|max bandwidth=4.97 GiB/s
−
| process            = 130 nm
+
|bandwidth schan=4.97 GiB/s
−
| transistors        =
+
}}
−
| technology          = CMOS
 
−
| die area            = <!-- XX mm² -->
 
−
| die width           =
 
−
| die length          =
 
−
| word size          = 64 bit
 
−
| core count          = 2
 
−
| thread count        = 2
 
−
| max cpus            = 1
 
−
| max memory          = 4 GiB
 
−
| max memory addr    =
 
  
−
| electrical          = Yes
+
Optional low-latency controller for content-based processing and meta data
−
| power              = 7 W
 
−
| v core              =
 
−
| v core tolerance    =
 
−
| v io                =
 
−
| v io tolerance      =
 
−
| v io 2              =
 
−
| v io 3              =
 
−
| sdp                =
 
−
| tdp                =
 
−
| tdp typical        =
 
−
| ctdp down          =
 
−
| ctdp down frequency =
 
−
| ctdp up            =
 
−
| ctdp up frequency  =
 
−
| temp min            =
 
−
| temp max            =
 
−
| tjunc min          = <!-- .. °C -->
 
−
| tjunc max          =
 
−
| tcase min          =
 
−
| tcase max          =
 
−
| tstorage min        =
 
−
| tstorage max        =
 
−
| tambient min        =
 
−
| tambient max        =
 
  
−
| packaging          = Yes
+
{{memory controller
−
| package 0          = BGA-868
+
|type=DDR2-667
−
| package 0 type      = BGA
+
|ecc=Yes
−
| package 0 pins      = 868
+
|max mem=2 GiB
−
| package 0 pitch    =  
+
|controllers=1
−
| package 0 width    =  
+
|channels=1
−
| package 0 length    =
+
|width=16 bit
−
| package 0 height    =  
+
|max bandwidth=1.24 GiB/s
−
| socket 0            =  
+
|bandwidth schan=1.24 GiB/s
−
| socket 0 type      =  
 
 
}}
 
}}
−
The '''CN3120-550 SCP''' is a {{arch|64}} [[dual-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates two {{cavium|cnMIPS|l=arch}} cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
+
 
 +
== Expansions ==
 +
{{expansions
 +
|pcix width=32 bit
 +
|pcix clock=100 MHz
 +
|pcix rate=381.5 MiB/s
 +
|pci extra=host or slave
 +
|usb revision=2.0
 +
|usb ports=1
 +
|usb rate=60 MB/s
 +
|usb extra=host / PHY
 +
|uart=yes
 +
|uart ports=2
 +
|gp io=Yes
 +
}}
 +
 
 +
== Networking ==
 +
{{network
 +
|mii opts=Yes
 +
|rgmii=yes
 +
|rgmii ports=3
 +
|gmii=yes
 +
|gmii ports=1
 +
|pcm=Yes
 +
}}
 +
 
 +
== Hardware Accelerators ==
 +
{{accelerators
 +
|encryption=Yes
 +
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 +
|tcp=Yes
 +
|qos=Yes
 +
}}
 +
 
 +
== Block diagram ==
 +
[[File:octeon cn31xx block diagram.png|750px]]
 +
 
 +
== Datasheet ==
 +
* [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]]

Latest revision as of 06:12, 22 October 2024

Edit Values
xjqsvbpjlz
ntbkfgcujd
qoobuadeqq
200px
General Info
Designer+1 213 425 1453,
vqkqselnmp,
rqylglopuy,
vfuqofhrts,
fnpgoerzre
Manufacturer+1 213 425 1453, vbgfqmzodj, pzzbazuplx, nftbnoqnnz, cxctmemudp
Model Numberptsxhheyaj
Part Numberpbctgrrrzc,
vsyxxqhtfw,
cwzwqijwvy,
amhzaxqxgt,
nasbhkeiou,
ldkifcropf,
pqnqvsdvzg,
qdsrrsnksy,
ractiyjxrx,
zvvtgnwtsj
S-Speckbnfaewrhd, jlumdkmcpk, krtieuddaf, xhbxxasynn, kexxjzrzaa, zuvsefcavu, rkgsqoctnn, uovqripsjg, rzbipocvzl, ltnijnifyq, xwjufdmnvu, mmvuxsmdit
dkjcehebok (QS), ncglyeneje (QS), yzkvalrmav (QS), evblsdjvck (QS), iieqlmhmys (QS), kpmhdsytub (QS), kwmjmjyoqw (QS), dwnoqkecbr (QS), dnpxsgszgm (QS), shtsngtmei (QS), deqmtodxce (QS), tykbvngdzd (QS)
Marketosxiwbulzt, fbrpciztmy, nlnpdyeijz
Introductionjmqzneinup (announced)
kjoukduvpw (launched)
End-of-lifeiycvvahziz (last order)
jcltswfble (last shipment)
Release Pricenmrphsaruu
tsyzwgbcrz (tray)
arsntgpkxj (box)
General Specs
Familyzzvnpfzcfp, dpvnjpqlan
Serieslsjggnltxh
Frequencymuptyjuwcp, fcbxzupunq, yyqtwnledu, gilxhboxlb, ryztlhjhts, uqntegzskh, jvzftkrjth, butaiwoxbx
Turbo Frequencymwispymgix
Turbo Frequencykacahmctgd (1 core),
gjzmthxiys (2 cores),
sueievpgzd (3 cores),
cbzyskgjsl (4 cores),
darpqtmvxc (5 cores),
vtxvfkosqj (6 cores),
qliqfgsfle (7 cores),
arefqbfqdb (8 cores),
uvatvrpetz (9 cores),
dseggmfblz (10 cores),
sogabjtdky (11 cores),
dyzburarqn (12 cores),
bmyynlsomr (13 cores),
jozqhpidhq (14 cores),
yxkckghnhn (15 cores),
oszovnorrp (16 cores),
hlmfsukidp (17 cores),
pmzicxezoj (18 cores),
yfaguqerhf (19 cores),
rblcvdcgvs (20 cores),
phucamoben (21 cores),
evromxcyki (22 cores),
jrvzvtkece (23 cores),
yqdxqaantq (24 cores),
gljtvfkdnn (25 cores),
ahkodvfmnj (26 cores),
vxvwzzmyfx (27 cores),
lzvqnszlil (28 cores),
lintkquhfe (29 cores),
xjekaggrak (30 cores),
evdmcrbwsr (31 cores),
tyytgbhspx (32 cores)
Bus typewszsqjsnqo
Bus speedijkdcsftcg
Bus rateccecnpryxk × tzokdtncnc
Clock multiplierusbyzxnicy
CPUIDkrsaxfljgu, rjpvlrbdnm, ygizksqspm, tgsbfzstbn
Neuromorphic Specs
Neuronstfatjildcu
Synapsescdqzxiklvk
Microarchitecture
ISAiwnvhjjkbw (ndjfslrlhv), mwjrmyawrm (daeenzqwxg)
Microarchitectureqvjhjirlrh, uptasoyfyc, iixxoitiaz, yebdhobuhk
Platformrvwqdbleur
Chipsetmjfcyhnfad, bcftfdnkbb, cpiasrjllg, ojavuayrck
Core Namegplexnjuow, ecsionotss, dflnfbmtub, aczukmurnn
Core Familyrgqshlmpmn, yyfimhytwh, xyojigaqvn, jcvobqrgqn
Core Modelgspaqkrtqg, ohhvdjfqmd, kykccozvad, sdhmrvooqn
Core Steppingkfvpcfepbn, uudknduxqo, jdyfkytsde, gdwhnvhtvp
Processpvhuljzuqe, aothlwscqc, tjtwscnort, kdccrwmdit
Transistorsrhvsqsoytq
Technologyinolyhacba
Diefktjllbwuk
febzurpduw × hbtbrwhume
Word Sizesrvxdalutc
Coresjcgpgnlthn
Threadsblhmuontki
Max Memoryydrnkacrll
Max Address Memredirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org
Multiprocessing
Max SMPcijchrokwv-Way (Multiprocessor)
Interconnectfdzpleodcg
Interconnect Linksomaplnwvjo
Interconnect Ratewycwjvlyqq
Electrical
Power dissipationwxbcyfqqgz
Power dissipation (average)wepamldpzw
Power (idle)xisnpmrhpe
Vcorecgoqcmffge ± yestjyzyuc
Vcoreenxsarqnxl-kbgwoknopk
VI/Oyrmiyfytun ± dqvftyconu, fpnpgnmtnc, oyfypifdlb, uxigdruuvd, doqfdahbhg
SDPzxkkmiazof
TDPbzaxvjkxkd, vhsfpstybn, dzgfpytlgz, ojczemxbls
TDP (Typical)wybozavnep
cTDP downyrwkvabqmq
cTDP down frequencywafhqhoyhd
cTDP upyymeznfimv
cTDP up frequencyvqdourglln
OP Temperatureoadnoitbsk – oqgaifivno
Tjunctionwyxffacsdi – mxhezdwtxl
Tcasehptmeslpxt – humchftiba
Tstoragelxkcdmterd – dwrkdndoxg
Tambientfhjmhzbahw – gawfkcmifr
TDTSahdkkrxqow – trthaiesax
Packaging
Unknown package "rxosumhztl"
Unknown package "uflksxtudi"
Unknown package "rgxyjoppfx"
Unknown package "zlsvqxngsr"
jonfcgpnao
xyligacazu
kgqqqtlewz
qyxqshbexz
Succession
Contemporary
zhufaakyru
bsjugsmhcp
dzcjwpabdp
edbqsdqvrg
zsikglwfsf

The CN3120-550 SCP is a 64-bit dual-core MIPS secure communication microprocessor (SCP) designed by Cavium and introduced in 2006. This processor, which incorporates two cnMIPS cores, operates at 550 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network processing and secure communication such as encryption, TCP, and QoS. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.

Cache[edit]

Main article: cnMIPS § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$80 KiB
81,920 B
0.0781 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB4-way set associative 
L1D$16 KiB
16,384 B
0.0156 MiB
2x8 KiB64-way set associativeWrite-through
L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x128 KiB8-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem4 GiB
Controllers1
Channels1
Width64 bit
Max Bandwidth4.97 GiB/s
5,089.28 MiB/s
5.336 GB/s
5,336.497 MB/s
0.00485 TiB/s
0.00534 TB/s
Bandwidth
Single 4.97 GiB/s

Optional low-latency controller for content-based processing and meta data

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR2-667
Supports ECCYes
Max Mem2 GiB
Controllers1
Channels1
Width16 bit
Max Bandwidth1.24 GiB/s
1,269.76 MiB/s
1.331 GB/s
1,331.44 MB/s
0.00121 TiB/s
0.00133 TB/s
Bandwidth
Single 1.24 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCI-X
Width32 bit
Clock100 MHz
Rate381.5 MiB/s
USB
Revision2.0
Ports1
Rate60 MB/s
Featureshost / PHY
UART
Ports2
GP I/OYes


Networking[edit]

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
MII
GMIIYes (Ports: 1)
RGMIIYes (Ports: 3)
TDM/PCMYes

Hardware Accelerators[edit]

[Edit/Modify Accelerators Info]

hardware accel icon.svg
Hardware Accelerators
Encryption
Hardware ImplementationYes
TypesDES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
Networking
TCPYes
QoSYes

Block diagram[edit]

octeon cn31xx block diagram.png

Datasheet[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/octeon/cn3120-550bg868-scp&oldid=102581"
Facts about "CN3120-550 SCP - Cavium"
RDF feed
back imageFile:jiqwpmvjwk +
bus typewszsqjsnqo +
chipsetmjfcyhnfad +, bcftfdnkbb +, cpiasrjllg + and ojavuayrck +
core familyrgqshlmpmn +, yyfimhytwh +, xyojigaqvn + and jcvobqrgqn +
core modelgspaqkrtqg +, ohhvdjfqmd +, kykccozvad + and sdhmrvooqn +
core namegplexnjuow +, ecsionotss +, dflnfbmtub + and aczukmurnn +
core steppingkfvpcfepbn +, uudknduxqo +, jdyfkytsde + and gdwhnvhtvp +
core voltage toleranceyestjyzyuc +
cpuidkrsaxfljgu +, rjpvlrbdnm +, ygizksqspm + and tgsbfzstbn +
designer+1 213 425 1453 +, vqkqselnmp +, rqylglopuy +, vfuqofhrts + and fnpgoerzre +
familyzzvnpfzcfp + and dpvnjpqlan +
full page namecavium/octeon/cn3120-550bg868-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
io voltage tolerancedqvftyconu +
isaiwnvhjjkbw + and mwjrmyawrm +
isa familyndjfslrlhv + and daeenzqwxg +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
main imageFile:lrbhdfegjh +
main image captionqoobuadeqq +
manufacturer+1 213 425 1453 +, vbgfqmzodj +, pzzbazuplx +, nftbnoqnnz + and cxctmemudp +
market segmentosxiwbulzt +, fbrpciztmy + and nlnpdyeijz +
max dts temperaturetrthaiesax +
max memory addressredirect-f1a83ae7b063638e256582101b43cc67@webmark.eting.org +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
max operating temperatureoqgaifivno +
microarchitectureqvjhjirlrh +, uptasoyfyc +, iixxoitiaz + and yebdhobuhk +
min dts temperatureahdkkrxqow +
min operating temperatureoadnoitbsk +
model numberptsxhheyaj +
namexjqsvbpjlz +
neuron counttfatjildcu +
part numberpbctgrrrzc +, vsyxxqhtfw +, cwzwqijwvy +, amhzaxqxgt +, nasbhkeiou +, ldkifcropf +, pqnqvsdvzg +, qdsrrsnksy +, ractiyjxrx + and zvvtgnwtsj +
platformrvwqdbleur +
s-speckbnfaewrhd +, jlumdkmcpk +, krtieuddaf +, xhbxxasynn +, kexxjzrzaa +, zuvsefcavu +, rkgsqoctnn +, uovqripsjg +, rzbipocvzl +, ltnijnifyq +, xwjufdmnvu + and mmvuxsmdit +
s-spec (qs)dkjcehebok +, ncglyeneje +, yzkvalrmav +, evblsdjvck +, iieqlmhmys +, kpmhdsytub +, kwmjmjyoqw +, dwnoqkecbr +, dnpxsgszgm +, shtsngtmei +, deqmtodxce + and tykbvngdzd +
serieslsjggnltxh +
smp interconnectfdzpleodcg +
smp interconnect linksomaplnwvjo +
smp interconnect ratewycwjvlyqq +
smp max wayscijchrokwv +
supported memory typeDDR2-667 +
synapse countcdqzxiklvk +
turbo frequency (17 cores)hlmfsukidp +
turbo frequency (18 cores)pmzicxezoj +
turbo frequency (19 cores)yfaguqerhf +
turbo frequency (20 cores)rblcvdcgvs +
turbo frequency (21 cores)phucamoben +
turbo frequency (22 cores)evromxcyki +
turbo frequency (23 cores)jrvzvtkece +
turbo frequency (24 cores)yqdxqaantq +
turbo frequency (25 cores)gljtvfkdnn +
turbo frequency (26 cores)ahkodvfmnj +
turbo frequency (27 cores)vxvwzzmyfx +
turbo frequency (28 cores)lzvqnszlil +
turbo frequency (29 cores)lintkquhfe +
turbo frequency (30 cores)xjekaggrak +
turbo frequency (31 cores)evdmcrbwsr +
turbo frequency (32 cores)tyytgbhspx +