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Information for "cavium/octeon plus/cn5830-900bg1521-scp"

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Display titleCN5830-900 SCP - Cavium
Default sort keyCN5830-900 SCP, Cavium
Page length (in bytes)3,732
Page ID12257
Page content languageEnglish (en)
Page content modelwikitext
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Number of redirects to this page6
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Page creatorChipIt (talk | contribs)
Date of page creation00:08, 15 December 2016
Latest editorChippyBot (talk | contribs)
Date of latest edit16:12, 13 December 2017
Total number of edits11
Total number of distinct authors2
Recent number of edits (within past 90 days)0
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CN5830-900 SCP - Cavium#package +
base frequency900 MHz (0.9 GHz, 900,000 kHz) +
core count4 +
designerCavium +
familyOCTEON Plus +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus/cn5830-900bg1521-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size192 KiB (196,608 B, 0.188 MiB) +
l1d$ description64-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateFebruary 2007 +
main imageFile:octeon plus chip.png +
manufacturerTSMC +
market segmentNetwork +
max cpu count1 +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN5830-900 SCP +
nameCavium CN5830-900 SCP +
packageFCBGA-1521 +
part numberCN5830-900BG1521-SCP +
process90 nm (0.09 μm, 9.0e-5 mm) +
seriesCN58xx +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +