Information for "cavium/octeon/cn3005-500bg350-cp"

Basic information

Display title	CN3005-500 CP - Cavium
Default sort key	CN3005-500 CP, Cavium
Page length (in bytes)	3,891
Page ID	11995
Page content language	English (en)
Page content model	wikitext
Indexing by robots	Allowed
Number of redirects to this page	6
Counted as a content page	Yes
Number of subpages of this page	0 (0 redirects; 0 non-redirects)

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Page creator	ChipIt (talk \| contribs)
Date of page creation	05:16, 8 December 2016
Latest editor	ChippyBot (talk \| contribs)
Date of latest edit	15:10, 13 December 2017
Total number of edits	22
Total number of distinct authors	2
Recent number of edits (within past 90 days)	0
Recent number of distinct authors	0

Transcluded templates (15)	Templates used on this page: Template:accelerators (edit) Template:arch (view source) (protected) Template:cache size (view source) (protected) Template:cavium (edit) Template:cavium title (edit) Template:chip (view source) (protected) Template:expansions (edit) Template:istrue (view source) (protected) Template:link-cavium (edit) Template:main (view source) (protected) Template:memory controller (edit) Template:network (edit) Template:url parse anchor (view source) (protected) Template:url parse article (view source) (protected) Module:chip (view source)

base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
core count	1 +
core name	cnMIPS +
designer	Cavium +
family	OCTEON +
first announced	January 30, 2006 +
first launched	May 1, 2006 +
full page name	cavium/octeon/cn3005-500bg350-cp +
has ecc memory support	false +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description	64-way set associative +
l1d$ size	8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description	2-way set associative +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	2-way set associative +
l2$ size	0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +
ldate	May 1, 2006 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max cpu count	1 +
max memory	2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth	0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) +
max memory channels	1 +
microarchitecture	cnMIPS +
model number	CN3005-500 CP +
name	Cavium CN3005-500 CP +
part number	CN3005-500BG350-CP +
power dissipation	4 W (4,000 mW, 0.00536 hp, 0.004 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
series	CN3000 +
smp max ways	1 +
supported memory type	DDR2-533 +
technology	CMOS +
thread count	1 +
word size	64 bit (8 octets, 16 nibbles) +