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{{x86 title|Extensions}}{{x86 isa main}} | {{x86 title|Extensions}}{{x86 isa main}} | ||
The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions. | The [[x86]] [[instruction set architecture|ISA]] has gone through numerous iterations that added new [[instructions]] to performs specific tasks. These collections of new instructions are grouped into '''extensions'''. Different microprocessor models have different levels of support for certain extensions. | ||
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== Timeline == | == Timeline == | ||
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| [[1999]] || {{\|EMMX}} || {{intel|P6|l=arch}} || Extended MMX; an extension to MMX | | [[1999]] || {{\|EMMX}} || {{intel|P6|l=arch}} || Extended MMX; an extension to MMX | ||
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− | | [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; wider {{x86|XMM}} registers offer better performance | + | | [[2001]] || {{x86|SSE2}} || {{intel|P6|l=arch}} || Attempt to replace the original {{\|MMX}} instructions; use wider {{x86|XMM}} registers have offer better performance |
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| [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register | | [[2004]] || {{x86|SSE3}} || {{intel|Core|l=arch}} || Streaming SIMD Extensions 3; new instructions to operate on multiple values in the same register | ||
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| [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions | | [[2013]] || {{x86|AVX2}} || {{intel|Haswell|l=arch}} || Advanced Vector Extensions; additional instructions | ||
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− | | [[2014]] || {{x86|ADX}} || {{intel| | + | | [[2014]] || {{x86|ADX}} || {{intel|Haswell|l=arch}} || Multi-Precision Add-Carry Instruction extension |
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| [[2014]] || {{x86|RdRand}} || {{intel|Broadwell|l=arch}} || Part of Secure Key Technology extension (RdRand, RDSEED) | | [[2014]] || {{x86|RdRand}} || {{intel|Broadwell|l=arch}} || Part of Secure Key Technology extension (RdRand, RDSEED) | ||
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| [[2016]] || {{x86|SHA}} || {{intel|Goldmont|l=arch}} || SHA Extensions | | [[2016]] || {{x86|SHA}} || {{intel|Goldmont|l=arch}} || SHA Extensions | ||
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== Backwards compatibility == | == Backwards compatibility == | ||
− | Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's {{amd|K6-2|l=arch}} (i.e., {{x86|3DNow!}} & {{x86|E3DNow!}}) and those introduced by AMD's {{amd|Bulldozer|l=arch}} (i.e., {{x86|FMA4}}, {{x86|XOP}}, {{x86|LWP}}, and later {{x86|TBM}}) have been obsoleted. Note that {{amd|Zen|l=arch}}, at least for first stepping, still offered FMA4 support even though it's not indicated by {{x86|CPUID}}. | + | Generally speaking, all extensions are supported from their introductory date to present day. Extensions introduced by AMD's {{amd|K6-2|l=arch}} (i.e., {{x86|3DNow!}} & {{x86|E3DNow!}}) and those introduced by AMD's {{amd|Bulldozer|l=arch}} (i.e., {{x86|FMA4}}, {{x86|XOP}}, {{x86|LWP}}, and later {{x86|TBM}}) are have been obsoleted. Note that {{amd|Zen|l=arch}}, at least for first stepping, still offered FMA4 support even though it's not indicated by {{x86|CPUID}}. |
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[[Category:x86]] | [[Category:x86]] |