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:[[File:vnni-vpdpwssd.svg|600px]] | :[[File:vnni-vpdpwssd.svg|600px]] | ||
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Likewise, for 8-bit values, three instructions are needed - <code>VPMADDUBSW</code> which is used to multiply two 8-bit pairs and add them together, followed by a <code>VPMADDWD</code> with the value <code>1</code> in order to simply up-convert the 16-bit values to 32-bit values, followed by the <code>VPADDD</code> instruction which adds the result to an accumulator. | Likewise, for 8-bit values, three instructions are needed - <code>VPMADDUBSW</code> which is used to multiply two 8-bit pairs and add them together, followed by a <code>VPMADDWD</code> with the value <code>1</code> in order to simply up-convert the 16-bit values to 32-bit values, followed by the <code>VPADDD</code> instruction which adds the result to an accumulator. | ||
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== Detection == | == Detection == | ||
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{| class="wikitable" | {| class="wikitable" | ||
− | ! colspan="2" | {{x86|CPUID}} !! rowspan="2" | Instruction Set | + | ! colspan="2" | {{x86|CPUID}} !! rowspan="2" | Instruction Set |
|- | |- | ||
! Input !! Output | ! Input !! Output | ||
|- | |- | ||
− | | | + | | rowspan="14" | EAX=07H, ECX=0 || ECX[bit 11] || AVX512VNNI |
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− | | EAX=07H, ECX=0 || ECX[bit 11] || | ||
|} | |} | ||
== Microarchitecture support == | == Microarchitecture support == | ||
− | + | {| class="wikitable" | |
− | {{ | + | |- |
+ | ! Instructions !! Introduction | ||
+ | |- | ||
+ | | AVX512VNNI || {{intel|Cascade Lake|l=arch}} (server)<br>{{intel|Ice Lake (client)|Ice Lake|l=arch}} (client) | ||
+ | |} | ||
== Intrinsic functions == | == Intrinsic functions == | ||
− | <source lang= | + | <source lang=asm> |
− | + | # vpdpbusd | |
− | + | __m512i _mm512_dpbusd_epi32 (__m512i src, __m512i a, __m512i b) | |
− | + | __m512i _mm512_mask_dpbusd_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | |
− | + | __m512i _mm512_maskz_dpbusd_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | |
− | + | # vpdpbusds | |
− | + | __m512i _mm512_dpbusds_epi32 (__m512i src, __m512i a, __m512i b) | |
− | + | __m512i _mm512_mask_dpbusds_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | |
− | __m512i _mm512_dpbusd_epi32 (__m512i src, __m512i a, __m512i b) | + | __m512i _mm512_maskz_dpbusds_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) |
− | __m512i _mm512_mask_dpbusd_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | + | # vpdpwssd |
− | __m512i _mm512_maskz_dpbusd_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | + | __m512i _mm512_dpwssd_epi32 (__m512i src, __m512i a, __m512i b) |
− | + | __m512i _mm512_mask_dpwssd_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | |
− | + | __m512i _mm512_maskz_dpwssd_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | |
− | + | # vpdpwssds | |
− | + | __m512i _mm512_dpwssds_epi32 (__m512i src, __m512i a, __m512i b) | |
− | + | __m512i _mm512_mask_dpwssds_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | |
− | + | __m512i _mm512_maskz_dpwssds_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | |
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− | __m512i _mm512_dpbusds_epi32 (__m512i src, __m512i a, __m512i b) | ||
− | __m512i _mm512_mask_dpbusds_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | ||
− | __m512i _mm512_maskz_dpbusds_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | ||
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− | __m512i _mm512_dpwssd_epi32 (__m512i src, __m512i a, __m512i b) | ||
− | __m512i _mm512_mask_dpwssd_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | ||
− | __m512i _mm512_maskz_dpwssd_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | ||
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− | __m512i _mm512_dpwssds_epi32 (__m512i src, __m512i a, __m512i b) | ||
− | __m512i _mm512_mask_dpwssds_epi32 (__m512i src, __mmask16 k, __m512i a, __m512i b) | ||
− | __m512i _mm512_maskz_dpwssds_epi32 (__mmask16 k, __m512i src, __m512i a, __m512i b) | ||
</source> | </source> | ||
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* {{bib|hc|30|Intel}} | * {{bib|hc|30|Intel}} | ||
* Rodriguez, Andres, et al. "[https://ai.intel.com/nervana/wp-content/uploads/sites/53/2018/05/Lower-Numerical-Precision-Deep-Learning-Inference-Training.pdf Lower numerical precision deep learning inference and training]." Intel White Paper (2018). | * Rodriguez, Andres, et al. "[https://ai.intel.com/nervana/wp-content/uploads/sites/53/2018/05/Lower-Numerical-Precision-Deep-Learning-Inference-Training.pdf Lower numerical precision deep learning inference and training]." Intel White Paper (2018). | ||
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[[Category:x86_extensions]] | [[Category:x86_extensions]] |