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| − | === | + | === iCAP === |
{{see also|deep_trench_capacitor|l1=deep trench capacitor (DTC)}} | {{see also|deep_trench_capacitor|l1=deep trench capacitor (DTC)}} | ||
| − | TSMC | + | TSMC introduced iCAP in 2019. iCAPs are CoWoS [[deep_trench_capacitor|deep trench capacitors]] with a standard cell of 40 [[µm]] by 40 µm. While TSMC was unwilling to disclose the depth of the trenches, the [[capacitance density]] it is able to achieve is up to 340 [[nF/mm²]]. This translates to close to 20x improvement in capacitance density over the HD-MiM. Since multiple iCAPs can be used on a single interposer, the total capacitance possible is over 68 μF per Si interposer. iCAPs are high-yielding and have reported leakage currents below 1 fA/μm², including at high temperatures. TSMC reported very good PDN improvements with iCAP. Compared to equivalent CoWoS-based design without iCAP, TSMC is reporting just 0.05x the impedance and 0.45x the voltage droop. |
Since both [[through-silicon_via|TSVs]] and [[deep_trench_capacitor|DTCs]] co-exist on the same [[silicon wafer]], there are two ways to construct iCAPs. In the DTC-first approach, the deep trenches are formed prior to the TSV process which means special care must be taken to ensure the TSV thermal budget does not impact the DTCs. Alternatively, in a TSV-first flow, the TSV structures are formed first using the standard TSV process, but special care must be taken to mitigate TSV related issues such as the via protrusion phenomenon. Like HD-MiMs, a major benefit of DTC over package decaps is that they can be freely placed as close as possible to the desired circuit similar to on-chip decaps but with the added benefit that the deep trenches allow for much higher capacitance. Additionally, since this can be implemented across an entire 1700 mm2 interposer with all kinds of chips on top, the DTCs can be more finely designed to better address the PI of the chip above it. | Since both [[through-silicon_via|TSVs]] and [[deep_trench_capacitor|DTCs]] co-exist on the same [[silicon wafer]], there are two ways to construct iCAPs. In the DTC-first approach, the deep trenches are formed prior to the TSV process which means special care must be taken to ensure the TSV thermal budget does not impact the DTCs. Alternatively, in a TSV-first flow, the TSV structures are formed first using the standard TSV process, but special care must be taken to mitigate TSV related issues such as the via protrusion phenomenon. Like HD-MiMs, a major benefit of DTC over package decaps is that they can be freely placed as close as possible to the desired circuit similar to on-chip decaps but with the added benefit that the deep trenches allow for much higher capacitance. Additionally, since this can be implemented across an entire 1700 mm2 interposer with all kinds of chips on top, the DTCs can be more finely designed to better address the PI of the chip above it. | ||
