From WikiChip
Editing technology node
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{title|Technology Node}}{{lithography processes}} | {{title|Technology Node}}{{lithography processes}} | ||
− | The '''technology node''' (also '''process node''', '''process technology''' or simply '''node''') refers to a specific [[semiconductor manufacturing process]] and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name | + | The '''technology node''' (also '''process node''', '''process technology''' or simply '''node''') refers to a specific [[semiconductor manufacturing process]] and its design rules. Different nodes often imply different circuit generations and architectures. Generally, the smaller the technology node means the smaller the feature size, producing smaller transistors which are both faster and more power-efficient. Historically, the process node name refered to a number of different features of a transistor including the [[gate length]] as well as M1 half-pitch. Most recently, due to various marketing and discrepancies among foundries, the number itself has lost the exact meaning it once held. Recent technology nodes such as [[22 nm]], [[16 nm]], [[14 nm]], and [[10 nm]] refer purely to a specific generation of chips made in a particular technology. It does not correspond to any gate length or half pitch. Nevertheless the name convention has stuck and it's what the leading foundries call their nodes. |
− | + | In 2017 node names has been entirely overtaken by marketing, both [[Samsung]] and [[TSMC]] started calling each of their enhanced nodes new names - regardless of whether or not the node has had any kind of transistor shrink or [[BEOL]] scaling. Various enhancements have been announced: "12nm" ([[16 nm]] enhancement), "9nm", "8nm", "7nm", "6nm" ([[10 nm]]/[[7 nm]] [[DUV]]/[[EUV]] variants). [[Intel]] also introduces new enhanced processes nodes but they maintain a consistent naming scheme (e.g., "14nm", "14nm+", "14nm++") while reserving the 'common' node names for actual 0.7x shrinks (e.g., "14nm", "10nm", "7nm"). | |
== Nomenclature == | == Nomenclature == | ||
Line 13: | Line 13: | ||
<div style="display:inline-block; float: left; padding: 10px;">[[File:tech node.svg|100px]]</div> | <div style="display:inline-block; float: left; padding: 10px;">[[File:tech node.svg|100px]]</div> | ||
− | The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while [[DRAM]] development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of [[technology scaling]]. This continued to be the case well into the 2000s. The [[International Technology Roadmap for Semiconductors]] (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for [[Flash]], [[DRAM]], and [[MPU]]/[[ | + | The term itself, as we know it today, dates back to the 1990s where microprocessors development was driven by higher frequency while [[DRAM]] development was dominated by the evergrowing demand for higher capacities. Since higher capacities were achieved through higher density, it was DRAM that became the driver of [[technology scaling]]. This continued to be the case well into the 2000s. The [[International Technology Roadmap for Semiconductors]] (ITRS) provides the semiconductor industry with guidance and assistance with various technology nodes. By 2006, as microprocessors started dominating the technology scaling, ITRS replaced the term with a number of separate indicators for [[Flash]], [[DRAM]], and [[MPU]]/[[ASCI]]. |
The ITRS traditionally defined the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process. It is a common metric used to describe and differentiate the technologies used in [[fabricating]] [[integrated circuit]]s. | The ITRS traditionally defined the process node as the smallest half-pitch of contacted metal 1 lines allowed in the fabrication process. It is a common metric used to describe and differentiate the technologies used in [[fabricating]] [[integrated circuit]]s. | ||
Line 27: | Line 27: | ||
== Leading edge trend == | == Leading edge trend == | ||
− | As shrinking becomes more complex, requiring more capital, expertise, and resources, the number of companies capable of providing leading edge fabrication has been steadily dropping. As of | + | As shrinking becomes more complex, requiring more capital, expertise, and resources, the number of companies capable of providing leading edge fabrication has been steadily dropping. As of 2017, only four companies are now capable of fabricating [[integrated circuits]] on the most cutting edge process: [[Intel]], [[Samsung]], [[TSMC]], and [[GlobalFoundries]]. |
{| class="wikitable" style="text-align: center;" | {| class="wikitable" style="text-align: center;" | ||
− | ! colspan=" | + | ! colspan="10" | Number of Foundries with a Cutting Edge Logic Fab |
− | |- style="vertical-align: bottom | + | |- style="vertical-align: bottom;" |
| | | | ||
− | [[ | + | [[UMC]]<br> |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
[[STMicroelectronics]]<br> | [[STMicroelectronics]]<br> | ||
− | |||
[[IBM]]<br> | [[IBM]]<br> | ||
− | |||
− | |||
[[AMD]]<br> | [[AMD]]<br> | ||
[[Samsung]]<br> | [[Samsung]]<br> | ||
Line 65: | Line 42: | ||
[[Intel]] | [[Intel]] | ||
| | | | ||
− | + | UMC<br> | |
− | + | STMicroelectronics<br> | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
IBM<br> | IBM<br> | ||
− | |||
− | |||
AMD<br> | AMD<br> | ||
Samsung<br> | Samsung<br> | ||
Line 93: | Line 50: | ||
Intel | Intel | ||
| | | | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
UMC<br> | UMC<br> | ||
− | + | STMicroelectronics<br> | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
IBM<br> | IBM<br> | ||
− | |||
− | |||
[[GlobalFoundries]]<br> | [[GlobalFoundries]]<br> | ||
Samsung<br> | Samsung<br> | ||
Line 130: | Line 58: | ||
Intel | Intel | ||
| | | | ||
− | + | UMC<br> | |
− | + | STMicroelectronics<br> | |
− | |||
− | |||
− | |||
− | |||
− | |||
IBM<br> | IBM<br> | ||
− | + | GlobalFoundries<br> | |
− | |||
− | |||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
| | | | ||
− | + | UMC<br> | |
− | + | STMicroelectronics<br> | |
− | |||
IBM<br> | IBM<br> | ||
− | + | GlobalFoundries<br> | |
− | |||
− | |||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Line 157: | Line 75: | ||
| | | | ||
IBM<br> | IBM<br> | ||
− | + | GlobalFoundries<br> | |
− | |||
− | |||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
| | | | ||
− | + | GlobalFoundries<br> | |
− | |||
− | |||
− | |||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
| | | | ||
− | |||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
| | | | ||
+ | GlobalFoundries<br> | ||
Samsung<br> | Samsung<br> | ||
TSMC<br> | TSMC<br> | ||
Intel | Intel | ||
| | | | ||
− | + | Future | |
− | |||
− | |||
|- | |- | ||
− | |||
| [[130 nm]] | | [[130 nm]] | ||
| [[90 nm]] | | [[90 nm]] | ||
Line 197: | Line 107: | ||
| [[5 nm]] | | [[5 nm]] | ||
|} | |} | ||
− | |||
− |