From WikiChip
Editing scaling booster

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 7: Line 7:
 
== Boosters ==
 
== Boosters ==
 
=== Track Reduction ===
 
=== Track Reduction ===
−
{{main|track reduction|l1=Track Reduction}}
+
{{empty section}}
−
'''Track Reduction''' (also called '''Fin Depopulation''' in the context of [[FinFET]]) is a technique for improving the density of the [[standard cell library]] by reducing the number of fins per [[FinFET]] transistor or the height of the active N or P region. By reducing the height of the active region, the number of tracks is reduced thereby reducing the height of the [[standard cell]] and ultimately increasing the transistor density of the chip. In the case of FinFET, fin depopulation results in energy reduction but also performance reduction.
 
−
 
 
 
=== Self-Aligned Contacts (SAC) ===
 
=== Self-Aligned Contacts (SAC) ===
−
{{main|self-aligned contact|l1=self-aligned contact (SAC)}}
+
{{empty section}}
−
As nodes continued to shrink the various features, the landing area for the gate contacts shrunk to a point where decreasing the pitch any further would result in uneconomical yield loss. '''Self-aligned contact''' ('''SAC''') is a process enhancement technique that loosens up the alignment tolerances associated with the landing area of the [[gate contacts]], thereby allowing the contacted gate pitch to shrink further while improving the yield by preventing yield loss due to the contact shorting the gate.
 
−
 
 
−
:[[File:cpp scaling with sac.svg|400px]]
 
−
 
 
 
=== Self-Aligned Vias (SAV) ===
 
=== Self-Aligned Vias (SAV) ===
 
{{empty section}}
 
{{empty section}}
−
 
 
=== Single Diffusion Break (SDB) ===
 
=== Single Diffusion Break (SDB) ===
−
{{main|single diffusion break|l1=Single Diffusion Break (SDB)}}
+
{{empty section}}
−
Historically, cell boundaries were padded with an additional dummy gate right after the active diffusion regions, at fin ends, for better cell control. As node scaling continued, due to cell height reduction, the portion of the area that makes up the dummy gate grew. '''Single Dummy Gate''' ('''SDG''') or '''Single Diffusion Break''' ('''SDB''') is a process enhancement technique that eliminates the extra padding around the cell edge when packaging multiple cells, thereby reducing the effective transistor density at the block and macro level.
 
−
 
 
−
:[[File:ttt-cell-scaling-sdb.svg|400px]]
 
−
 
 
 
==== Mixed Diffusion Break (MDB) ====
 
==== Mixed Diffusion Break (MDB) ====
 
{{empty section}}
 
{{empty section}}
−
 
 
=== Contact Over Active Gate (COAG) ===
 
=== Contact Over Active Gate (COAG) ===
−
{{main|contact over active gate|l1=Contact Over Active Gate (COAG)}}
+
{{empty section}}
−
Typically, the area between the end of the nMOS and pMOS devices is used as the gate contact hit location. In an effort to reduce cell height, engineering effort was placed on reducing that region. '''Self-aligned Contact Over Active Gate''' ('''COAG''') is a process enhancement technique that eliminates the need to land the contact outside of the active gate, allowing the gate contact to land directly over the active gate, thereby reducing the amount of space the end-to-end (ETE) spacing between devices.
 
−
 
 
−
:[[File:scaling with coag.svg|400px]]
 
−
 
 
 
=== Buried Power Rail (BPR) ===
 
=== Buried Power Rail (BPR) ===
 
{{empty section}}
 
{{empty section}}
−
 
 
=== SuperVia ===
 
=== SuperVia ===
−
SuperVia is the concept of having a Via etch through 2 metal dielectrics stack instead of landing on the bottom metal to and have another via on the bottom metal.  This helps with routing concerns and improves scaling.
+
{{empty section}}
−
 
 
 
=== Fully Self Aligned Via (FSAV) ===
 
=== Fully Self Aligned Via (FSAV) ===
 
{{empty section}}
 
{{empty section}}
−
 
 
=== Self-Aligned Block (SAB) ===
 
=== Self-Aligned Block (SAB) ===
 
{{empty section}}
 
{{empty section}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

This page is a member of 1 hidden category:

Retrieved from "https://en.wikichip.org/wiki/scaling_booster"