Editing scaling booster

{{title|Scaling Booster}}
A '''scaling booster''' is an enhancement made to a [[process node]] beyond classical scaling vectors in order to allow [[Moore's Law]] device scaling to continue or accelerate.

== Overview ==
As [[process nodes]] continues to shrink, classical scaling vectors (e.g., [[gate pitch]]) becomes increasingly challenging. There are multiple reasons for this including electrostatics in the FEOL, RC delays in the BEOL, as well as general routing challenges. Scaling boosters have been introduced in order to aid traditional scaling vectors through various modifications and enhancements. Scaling boosters may be part of the process technology flow itself or as part of the standard library as part of the design-technology co-optimization (DTCO). By combining scaling boosters with slightly less aggressive classical scaling vectors, a process node can achieve similar transistors density while keeping the process cost in check.

== Boosters ==
=== Track Reduction ===
{{main|track reduction|l1=Track Reduction}}
'''Track Reduction''' (also called '''Fin Depopulation''' in the context of [[FinFET]]) is a technique for improving the density of the [[standard cell library]] by reducing the number of fins per [[FinFET]] transistor or the height of the active N or P region. By reducing the height of the active region, the number of tracks is reduced thereby reducing the height of the [[standard cell]] and ultimately increasing the transistor density of the chip. In the case of FinFET, fin depopulation results in energy reduction but also performance reduction.

=== Self-Aligned Contacts (SAC) ===
{{main|self-aligned contact|l1=self-aligned contact (SAC)}}
As nodes continued to shrink the various features, the landing area for the gate contacts shrunk to a point where decreasing the pitch any further would result in uneconomical yield loss. '''Self-aligned contact''' ('''SAC''') is a process enhancement technique that loosens up the alignment tolerances associated with the landing area of the [[gate contacts]], thereby allowing the contacted gate pitch to shrink further while improving the yield by preventing yield loss due to the contact shorting the gate.

:[[File:cpp scaling with sac.svg|400px]]

=== Self-Aligned Vias (SAV) ===
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=== Single Diffusion Break (SDB) ===
{{main|single diffusion break|l1=Single Diffusion Break (SDB)}}
Historically, cell boundaries were padded with an additional dummy gate right after the active diffusion regions, at fin ends, for better cell control. As node scaling continued, due to cell height reduction, the portion of the area that makes up the dummy gate grew. '''Single Dummy Gate''' ('''SDG''') or '''Single Diffusion Break''' ('''SDB''') is a process enhancement technique that eliminates the extra padding around the cell edge when packaging multiple cells, thereby reducing the effective transistor density at the block and macro level.

:[[File:ttt-cell-scaling-sdb.svg|400px]]

==== Mixed Diffusion Break (MDB) ====
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=== Contact Over Active Gate (COAG) ===
{{main|contact over active gate|l1=Contact Over Active Gate (COAG)}}
Typically, the area between the end of the nMOS and pMOS devices is used as the gate contact hit location. In an effort to reduce cell height, engineering effort was placed on reducing that region. '''Self-aligned Contact Over Active Gate''' ('''COAG''') is a process enhancement technique that eliminates the need to land the contact outside of the active gate, allowing the gate contact to land directly over the active gate, thereby reducing the amount of space the end-to-end (ETE) spacing between devices.

=== Buried Power Rail (BPR) ===
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=== SuperVia ===
SuperVia is the concept of having a Via etch through 2 metal dielectrics stack instead of landing on the bottom metal to and have another via on the bottom metal.  This helps with routing concerns and improves scaling.

=== Fully Self Aligned Via (FSAV) ===
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=== Self-Aligned Block (SAB) ===
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