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== Overview == | == Overview == | ||
− | By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}} | + | By default, only the {{risc-v|integer base|core ISA}} must be implemented presenting great opportunity for area and energy optimization. However, additional functionality is sometimes desired. RISC-V comes with a series of standard extensions that enable additional functionality beyond the {{risc-v|integer base|core ISA}}. Extensions can be implemented and omitted as desired. Those extensions are: |
− | { | + | * '''{{risc-v|A}}''' - Atomic instructions |
− | + | * '''{{risc-v|B}}''' - Bit manipulation instructions | |
− | + | * '''{{risc-v|C}}''' - Compressed instructions | |
− | |- | + | * '''{{risc-v|D}}''' - Double-precision floating-point instructions |
− | + | * '''{{risc-v|F}}''' - Single-precision floating-point instructions | |
− | |- | + | * '''{{risc-v|J}}''' - Dynamically translated languages |
− | + | * '''{{risc-v|L}}''' - Decimal floating point instructions | |
− | |- | + | * '''{{risc-v|M}}''' - Integer multiplication and division instructions |
− | + | * '''{{risc-v|N}}''' - User-level interrupt instructions | |
− | |- | + | * '''{{risc-v|P}}''' - Packed-SIMD instructions |
− | + | * '''{{risc-v|Q}}''' - Quad-precision floating-point instructions | |
− | + | * '''{{risc-v|T}}''' - Transactional Memory instructions | |
− | + | * '''{{risc-v|V}}''' - Vector operations instructions | |
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