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Various highly complex methods for reducing the [[power consumption]] of a chip have been developed over the years such as [[Intel]]'s {{intel|SpeedStep}} (EIST) and [[AMD]]'s {{amd|Cool'n'Quiet}}. Those methods make use of various [[Dynamic Voltage and Frequency Scaling]] (DVFS) techniques in order to reduce the [[P-State|operating voltage and frequency]] when the processing power is not needed thereby greatly reducing the dynamic energy consumption. | Various highly complex methods for reducing the [[power consumption]] of a chip have been developed over the years such as [[Intel]]'s {{intel|SpeedStep}} (EIST) and [[AMD]]'s {{amd|Cool'n'Quiet}}. Those methods make use of various [[Dynamic Voltage and Frequency Scaling]] (DVFS) techniques in order to reduce the [[P-State|operating voltage and frequency]] when the processing power is not needed thereby greatly reducing the dynamic energy consumption. | ||
− | One problem that remains is the [[static power]] [[leakage]] that is always present in the system. '''Race-to-sleep''' attempts to address this issue by proposing that the highest frequency is used to complete the task as fast as possible, then | + | One problem that remains is the [[static power]] [[leakage]] that is always present in the system. '''Race-to-sleep''' attempts to address this issue by proposing that the highest frequency is used to complete the task as fast as possible, then once finish, drop back to very low power modes - often turning off or power gating the cores. Race-to-sleep attempts to reduce the delay in completing a task as much as possible in order to reduce the static power consumption, thereby consuming significantly less power overall. |
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[[category:power management mechanism]] | [[category:power management mechanism]] |