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=== Data Rates === | === Data Rates === | ||
<table class="wikitable"> | <table class="wikitable"> | ||
− | <tr><th> </th><th>[[#NVLink 1.0|NVLink 1.0]]</th><th>[[#NVLink 2.0|NVLink 2.0]]</th><th> [[#NVLink 3.0|NVlink 3 | + | <tr><th> </th><th>[[#NVLink 1.0|NVLink 1.0]]</th><th>[[#NVLink 2.0|NVLink 2.0]]</th><th> [[#NVLink 3.0|NVlink 3.0]]</th></tr> |
− | <tr><th>Signaling Rate</th><td>20 GT/s</td><td>25 GT/s</td><td>50 | + | <tr><th>Signaling Rate</th><td>20 GT/s</td><td>25 GT/s</td><td>50 GT/s</td></tr> |
− | <tr><th>Lanes/Link</th><td>8</td><td>8</td><td>4 | + | <tr><th>Lanes/Link</th><td>8</td><td>8</td><td>4</td></tr> |
− | <tr><th>Rate/Link</th><td>20 GB/s</td><td>25 GB/s</td><td> | + | <tr><th>Rate/Link</th><td>20 GB/s</td><td>25 GB/s</td><td>50 GB/s</td></tr> |
− | <tr><th>BiDir BW/Link</th><td>40 GB/s</td><td>50 GB/s</td><td> | + | <tr><th>BiDir BW/Link</th><td>40 GB/s</td><td>50 GB/s</td><td> 100 GB/s</td></tr> |
− | <tr><th>Links/Chip</th><td>4 (P100)</td><td>6 (V100)</td><td> 12 (A100) | + | <tr><th>Links/Chip</th><td>4 (P100)</td><td>6 (V100)</td><td> 12 (A100)</tr> |
− | <tr><th>BiDir BW/Chip</th><td>160 GB/s (P100)</td><td>300 GB/s (V100)</td><td>600 GB/s (A100 | + | <tr><th>BiDir BW/Chip</th><td>160 GB/s (P100)</td><td>300 GB/s (V100)</td><td>600 GB/s (A100)</td></tr> |
</table> | </table> | ||
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== References == | == References == | ||
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* IEEE HotChips 29 (HC29), 2017 | * IEEE HotChips 29 (HC29), 2017 | ||
* IEEE HotChips 28 (HC28), 2016 | * IEEE HotChips 28 (HC28), 2016 | ||
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[[category:nvidia]] | [[category:nvidia]] | ||
[[Category:interconnect_architectures]] | [[Category:interconnect_architectures]] |