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{{mips title|PRId register}}
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The '''Processor ID''' ('''PRId''') is a [[read-only register|read-only]], [[special-purpose register]] found in the [[MIPS32]] and [[MIPS64]] ISAs that can be queried to identify the [[MIPS]] CPU. The [[Processor ID]] should be unique for each instruction set or CPU control register change. The PRId is the 15th register in [[Coprocessor 0 - MIPS|Coprocessor 0]].
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The '''Processor ID''' ('''PRId''') is a [[read-only register|read-only]], [[special-purpose register]] found in the {{mips|MIPS32}} and {{mips|MIPS64}} ISAs that can be queried to identify the [[MIPS]] CPU. The [[Processor ID]] should be unique for each instruction set or CPU control register change. The PRId is the 15th register in {{mips|Coprocessor 0}}.
 
  
 
== Register layout ==
 
== Register layout ==
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The PRId is the 15th register in {{mips|Coprocessor 0}}. It contains company options, company ID, CPU ID, and revision ID.
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The PRId is the 15th register in [[Coprocessor 0 - MIPS|Coprocessor 0]]. It contains company options, company ID, CPU ID, and revision ID.
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
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| 0x020000 || Broadcom
 
| 0x020000 || Broadcom
 
|-
 
|-
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| 0x030000 || [[Alchemy]], [[AMD]], [[RMI]] ({{alchemy|Alchemy}} processors)
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| 0x030000 || Alchemy
 
|-
 
|-
 
| 0x040000 || Sibyte
 
| 0x040000 || Sibyte
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| 0x0c0000 || Netlogic
 
| 0x0c0000 || Netlogic
 
|-
 
|-
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| 0x0d0000 || [[Cavium]]
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| 0x0d0000 || Cavium
 
|-
 
|-
 
| 0xd00000 || Ingenic
 
| 0xd00000 || Ingenic
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|}
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|}
  
 
=== CPU ID ===
 
=== CPU ID ===
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|-
 
|-
 
| 0x0100 || R2000
 
| 0x0100 || R2000
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|-
 +
| 0x0100 || AU1 Rev1
 +
|-
 +
| 0x0200 || AU2 Rev2
 
|-
 
|-
 
| 0x0200 || R3000
 
| 0x0200 || R3000
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|-
 
|-
 
| 0x8200 || 20KC
 
| 0x8200 || 20KC
−
|-
 
−
| 0x8300 || 4Km or 4Kp
 
 
|-
 
|-
 
| 0x8400 || 4KEC
 
| 0x8400 || 4KEC
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| 0x9e00 || M14KEC
 
| 0x9e00 || M14KEC
 
|}
 
|}
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==== Sibyte ====
 
==== Sibyte ====
 
{| class="wikitable sortable"
 
{| class="wikitable sortable"
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|-
 
|-
 
| 0x0400 || SR71000
 
| 0x0400 || SR71000
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|}
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|}  
 
==== Broadcom ====
 
==== Broadcom ====
 
{| class="wikitable sortable"
 
{| class="wikitable sortable"
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! CPU ID !! CPU
 
! CPU ID !! CPU
 
|-
 
|-
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| 0x0200 || JZRISC
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| 0x0200 || JZRISC  
 
|}
 
|}
  
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| 0x1200 || NETLOGIC_XLP2XX
 
| 0x1200 || NETLOGIC_XLP2XX
 
|}
 
|}
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==== Alchemy ====
 
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{| class="wikitable sortable"
 
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! CPU ID !! CPU Core
 
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|-
 
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| 0x0100 || {{alchemy|Au1|l=arch}} Rev. 1
 
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|-
 
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| 0x0200 || {{alchemy|Au1|l=arch}} Rev. 2
 
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|}
 
−
 
 
=== Revision ===
 
=== Revision ===
 
The revision is a manufacturer dependent value which can be used to track silicon revisions.
 
The revision is a manufacturer dependent value which can be used to track silicon revisions.
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[[Category:MIPS]]
 
[[Category:MIPS]]
 
[[Category:MIPS32]]
 
[[Category:MIPS32]]
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[[Category:MIPS registers]]
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[[Category:MIPS register]]

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