Editing mips/mips32 instruction set

{{mips title|MIPS32 Instruction Set}}
{{ISA|
|name          =  MIPS32
|designer      =  [[MIPS Technologies, Inc.]]
|bits          =  32-bits
|introduced    =  1999
|version       =  Revision 5.3
|design        =  RISC
|type          =  Register-Register
|encoding      =  Fixed-length
|branching     =  Condition Register
|endianness    =  Bi-endian
|extensions    =  {{mips|SPECIAL2}}, {{mips|COP2}}, {{mips|LWC2}}, {{mips|SWC2}}, {{mips|LDC2}}, {{mips|SDC2}}
|application   =  {{mips|MIPS16e}}, {{mips|MCU}}, {{mips|SmartMIPS}}
|multimedia    =  {{mips|MIPS-3D}}
|gpr           =  32
|fpr           =  32
|spr           = {{mips|PRId register|PRId}}
}}

The '''MIPS32 instruction set''' is an instruction set standard published in 1999 that was promulgated by [[MIPS Technologies]] after its [[Wikipedia:demerger|demerger]] from [[Silicon Graphics]] in 1998. The MIPS32 instruction set was developed along side the {{mips|MIPS64 Instruction Set}} which includes 64-bit instructions. The MIP32 standard included {{mips|coprocessor 0}} control instructions for the first time. Today, the MIP32 instruction set is the most common MIPS instruction set, compatible with most {{mips|CPUs}}. Due to its relative simply, the MIP32 instruction set is also the most common instruction set thought in computer architecture university courses.

The latest MIPS32 revision is revision 5, which added a set of new memory-efficient operations for large memory footprint applications.

== History ==
The MIPS32 instruction set architecture was first published in 1999 by [[MIPS Technologies]] by it has demerged from [[Silicon Graphics]] in 1998. MIPS32 is largely a superset of the {{mips|MIPS II}} ISA.

=== Release 2 ===
Release 2 was first introduced in revision 1 of the MIPS32 ISA in 2002. Release 2 added 20 new instructions: {{mips|DI}}, {{mips|EHB}}, {{mips|EI}}, {{mips|EXT}}, {{mips|INS}}, {{mips|JALR.HB}}, {{mips|JR.HB}}, {{mips|MFHC1}}, {{mips|MFHC2}}, {{mips|MTHC1}}, {{mips|MTHC2}}, {{mips|RDHWR}}, {{mips|RDPGPR}}, {{mips|ROTR}}, {{mips|ROTRV}}, {{mips|SEB}}, {{mips|SEH}}, {{mips|SYNCI}}, {{mips|WRPGPR}}, and {{mips|WSBH}}. Release 2 also added support for 64-bit FPUs.

=== Release 3 ===
Release 3 was first introduced in revision 3 of the MIPS32 ISA in 2010. The release added the {{mips|JALX}} instruction.

=== Release 4 ===
Release 4 was skipped because MIPS Technologies was being auctioned off. Officially the reason was given as "Release 4 because the number four is considered by many to be inauspicious or unlucky".<ref>[http://withimagination.imgtec.com/index.php/mips-processors/continuing-evolution-of-the-mips-instruction-set-architecture#sthash.4uCPPXKz.dpuf The continuing evolution of the MIPS Instruction Set Architecture]</ref>

=== Release 5 ===
Release 5 was announced in late 2012. The release added a new set of instructions called '''Enhanced Virtual Addressing''' (EVA) to allow more efficient use of memory of larger footprint kernels. The following EVA Load/Store instructions were added: {{mips|LBE}}, {{mips|LBUE}}, {{mips|LHE}}, {{mips|LHUE}}, {{mips|LWE}}, {{mips|SBE}}, {{mips|SHE}}, {{mips|SWE}}, {{mips|CACHEE}}, {{mips|PREFE}}, {{mips|LLE}}, {{mips|SCE}}, {{mips|LWLE}}, {{mips|LWRE}}, {{mips|SWLE}}, {{mips|SWRE}}.

== Instructions list ==
Below is a list of the MIPS32 Instruction Set

* CPU Instructions
** [[#Arithmetic instructions|Arithmetic Instructions]]
** [[#Branch instructions|Branch Instructions]]
** [[#Jump instructions|Jump Instructions]]
** [[#Control instructions|Control Instructions]]
** [[#Memory control instructions|Memory Control Instructions]]
** [[#Logical instruction|Logical Instruction]]
** [[#Insert/Extract instructions|Insert/Extract Instructions]]
** [[#Move instructions|Move Instructions]]
** [[#Shift instructions|Shift Instructions]]
** [[#Trap instructions|Trap Instructions]]
* FPU Instructions
** [[#Arithmetic instructions|Arithmetic Instructions]]
** [[#Branch instructions|Branch Instructions]]
** [[#Compare instructions|Compare Instructions]]
** [[#Convert instructions|Convert Instructions]]
** [[#Memory control instructions|Memory Control Instructions]]
** [[#Move instructions|Move Instructions]]
* [[Coprocessor]] Instructions
** [[#Branch instructions|Branch Instructions]]
** [[#Execute instructions|Execute Instructions]]
** [[#Memory control instructions|Memory control Instructions]]
** [[#Move instructions|Move Instructions]]
* [[#Privileged instructions|Privileged Instructions]]
* [[#EJTAG instructions|EJTAG Instructions]]

=== Arithmetic instructions ===

{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|ADD}} || Add Word
|-
| {{mips|ADDI}} || Add Immediate Word
|-
| {{mips|ADDIU}} || Add Immediate Unsigned Word
|-
| {{mips|ADDU}} || Add Unsigned Word
|-
| {{mips|CLO}} || Count Leading Ones in Word
|-
| {{mips|CLZ}} || Count Leading Zeros in Word
|-
| {{mips|DIV}} || Divide Word
|-
| {{mips|DIVU}} || Divide Unsigned Word
|-
| {{mips|MADD}} || Multiply and Add Word to Hi, Lo
|-
| {{mips|MADDU}} || Multiply and Add Unsigned Word to Hi, Lo
|-
| {{mips|MSUB}} || Multiply and Subtract Word to Hi, Lo
|-
| {{mips|MSUBU}} || Multiply and Subtract Unsigned Word to Hi, Lo
|-
| {{mips|MUL}} || Multiply Word to GPR
|-
| {{mips|MULT}} || Multiply Word
|-
| {{mips|MULTU}} || Multiply Unsigned Word
|-
| {{mips|SEB}} || Sign-Extend Byte
|-
| {{mips|SEH}} || Sign-Extend Halftword
|-
| {{mips|SLT}} || Set on Less Than
|-
| {{mips|SLTI}} || Set on Less Than Immediate
|-
| {{mips|SLTIU}} || Set on Less Than Immediate Unsigned
|-
| {{mips|SLTU}} || Set on Less Than Unsigned
|-
| {{mips|SUB}} || Subtract Word
|-
| {{mips|SUBU}} || Subtract Unsigned Word
|}

=== Branch instructions ===
Note that all the likely branches have been obsoleted; they will be removed in future revisions of the MIPS32 architecture. Software is strongly discouraged from using these instructions.

{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|B}} || Unconditional Branch
|-
| {{mips|BAL}} || Branch and Link
|-
| {{mips|BEQ}} || Branch on Equal
|-
| {{mips|BGEZ}} || Branch on Greater Than or Equal to Zero
|-
| {{mips|BGEZAL}} || Branch on Greater Than or Equal to Zero and Link
|-
| {{mips|BGTZ}} || Branch on Greater Than Zero
|-
| {{mips|BLEZ}} || Branch on Less Than or Equal to Zero
|-
| {{mips|BLTZ}} || Branch on Less Than Zero
|-
| {{mips|BLTZAL}} || Branch on Less Than Zero and Link
|-
| {{mips|BNE}} || Branch on Not Equal
|-
| <strike>{{mips|BEQL}}</strike> || Branch on Equal Likely
|-
| <strike>{{mips|BGEZALL}}</strike> || Branch on Greater Than or Equal to Zero and Link Likely
|-
| <strike>{{mips|BGEZL}}</strike> || Branch on Greater Than or Equal to Zero Likely
|-
| <strike>{{mips|BGTZL}}</strike> || Branch on Greater Than Zero Likely
|-
| <strike>{{mips|BLEZL}}</strike> || Branch on Less Than or Equal to Zero Likely
|-
| <strike>{{mips|BLTZALL}}</strike> || Branch on Less Than Zero and Link Likely
|-
| <strike>{{mips|BLTZL}}</strike> || Branch on Less Than Zero Likely
|-
| <strike>{{mips|BNEL}}</strike> || Branch on Not Equal Likely
|}

=== Jump instructions ===

{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|J}} || Jump
|-
| {{mips|JAL}} || Jump and Link
|-
| {{mips|JALR}} || Jump and Link Register
|-
| [[JALR.HB  - MIPS|JALR.HB ]]|| Jump and Link Register with Hazard Barrier
|-
| {{mips|JALX}} || Jump and Link Exchange
|-
| {{mips|JR}} || Jump Register
|-
| {{mips|JR.HB}} || Jump Register with Hazard Barrier
|}

=== Control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|EHB}} || Execution Hazard Barrier
|-
| {{mips|NOP}} || No Operation
|-
| {{mips|PAUSE}} || Wait for LLBit to Clear
|-
| {{mips|SSNOP}} || Superscalar No Operation
|}

=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|LB}} ||  Load Byte
|-
| {{mips|LBE}} || Load Byte EVA
|-
| {{mips|LBU}} || Load Byte Unsigned
|-
| {{mips|LBUE}} || Load Byte Unsigned EVA
|-
| {{mips|LH}} || Load Halfword
|-
| {{mips|LHE}} || Load Halfword EVA
|-
| {{mips|LHU}} || Load Halfword Unsigned
|-
| {{mips|LHUE}} || Load Halfword Unsigned EVA
|-
| {{mips|LL}} || Load Linked Word
|-
| {{mips|LLE}} || Load Linked Word-EVA
|-
| {{mips|LW}} || Load Word
|-
| {{mips|LWE}} || Load Word EVA
|-
| {{mips|LWL}} || Load Word Left
|-
| {{mips|LWLE}} || Load Word Left EVA
|-
| {{mips|LWR}} || Load Word Right
|-
| {{mips|LWRE}} || Load Word Right EVA
|-
| {{mips|PREF}} || Prefetch
|-
| {{mips|PREFE}} || Prefetch-EVA
|-
| {{mips|SB}} || Store Byte
|-
| {{mips|SBE}} || Store Byte EVA
|-
| {{mips|SC}} || Store Conditional Word
|-
| {{mips|SCE}} || Store Conditional Word EVA
|-
| {{mips|SH}} || Store Halfword
|-
| {{mips|SHE}} || Store Halfword EVA
|-
| {{mips|SW}} || Store Word
|-
| {{mips|SWE}} || Store Word EVA
|-
| {{mips|SWL}} || Store Word Left
|-
| {{mips|SWLE}} || Store Word Left EVA
|-
| {{mips|SWR}} || Store Word Right
|-
| {{mips|SWRE}} || Store Word Right EVA
|-
| {{mips|SYNC}} || Synchronize Shared Memory
|-
| {{mips|SYNCI}} || Synchronize Caches to Make Instruction Writes Effective
|}

=== Logical instruction ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|AND}} || And
|-
| {{mips|ANDI}} || And Immediate
|-
| {{mips|LUI}} || Load Upper Immediate
|-
| {{mips|NOR}} || Not Or
|-
| {{mips|OR}} || Or
|-
| {{mips|ORI}} || Or Immediate
|-
| {{mips|XOR}} || Exclusive Or
|-
| {{mips|XORI}} || Exclusive Or Immediate
|}

=== Insert/Extract instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|EXT}} || Extract Bit Field
|-
| {{mips|INS}} || Insert Bit Field
|-
| {{mips|WSBH}} || Word Swap Bytes Within Halfwords
|}

=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|MFHI}} || Move From HI Register
|-
| {{mips|MFLO}} || Move From LO Register
|-
| {{mips|MOVF}} || Move Conditional on Floating Point False
|-
| {{mips|MOVN}} || Move Conditional on Not Zero
|-
| {{mips|MOVT}} || Move Conditional on Floating Point True
|-
| {{mips|MOVZ}} || Move Conditional on Zero
|-
| {{mips|MTHI}} || Move To HI Register
|-
| {{mips|MTLO}} || Move To LO Register
|-
| {{mips|RDHWR}} || Read Hardware Register
|}

=== Shift instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|ROTR}} || Rotate Word Right
|-
| {{mips|ROTRV}} || Rotate Word Right Variable
|-
| {{mips|SLL}} || Shift Word Left Logical
|-
| {{mips|SLLV}} || Shift Word Left Logical Variable
|-
| {{mips|SRA}} || Shift Word Right Arithmetic
|-
| {{mips|SRAV}} || Shift Word Right Arithmetic Variable
|-
| {{mips|SRL}} || Shift Word Right Logical
|-
| {{mips|SRLV}} || Shift Word Right Logical Variable
|}

=== Trap instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|BREAK}} || Breakpoint
|-
| {{mips|SYSCALL}} || System Call
|-
| {{mips|TEQ}} || Trap if Equal
|-
| {{mips|TEQI}} || Trap if Equal Immediate
|-
| {{mips|TGE}} || Trap if Greater or Equal
|-
| {{mips|TGEI}} || Trap if Greater of Equal Immediate
|-
| {{mips|TGEIU}} || Trap if Greater or Equal Immediate Unsigned
|-
| {{mips|TGEU}} || Trap if Greater or Equal Unsigned
|-
| {{mips|TLT}} || Trap if Less Than
|-
| {{mips|TLTI}} || Trap if Less Than Immediate
|-
| {{mips|TLTIU}} || Trap if Less Than Immediate Unsigned
|-
| {{mips|TLTU}} || Trap if Less Than Unsigned
|-
| {{mips|TNE}} || Trap if Not Equal
|-
| {{mips|TNEI}} || Trap if Not Equal Immediate
|}


== FPU instructions ==

=== Arithmetic instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|ABS.fmt}} || Floating Point Absolute Value
|-
| {{mips|ADD.fmt}} || Floating Point Add
|-
| {{mips|DIV.fmt}} || Floating Point Divide
|-
| {{mips|MADD.fmt}} || Floating Point Multiply Add
|-
| {{mips|MSUB.fmt}} || Floating Point Multiply Subtract
|-
| {{mips|MUL.fmt}} || Floating Point Multiply
|-
| {{mips|NEG.fmt}} || Floating Point Negate
|-
| {{mips|NMADD.fmt}} || Floating Point Negative Multiply Add
|-
| {{mips|NMSUB.fmt}} || Floating Point Negative Multiply Subtract
|-
| {{mips|RECIP.fmt}} || Reciprocal Approximation
|-
| {{mips|RSQRT.fmt}} || Reciprocal Square Root Approximation
|-
| {{mips|SQRT.fmt}} || Floating Point Square Root
|-
| {{mips|SUB.fmt}} || Floating Point Subtract
|}


=== Branch instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|BC1F}} || Branch on FP False
|-
| {{mips|BC1T}} || Branch on FP True
|-
| <strike>{{mips|BC1FL}}</strike> || Branch on FP False Likely
|-
| <strike>{{mips|BC1TL}}</strike> || Branch on FP True Likely
|}

=== Compare instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|C.cond.fmt}} || Floating Point Compare
|}

=== Convert instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|ALNV.PS}} || Floating Point Align Variable
|-
| {{mips|CEIL.L.fmt}} || Floating Point Ceiling Convert to Long Fixed Point
|-
| {{mips|CEIL.W.fmt}} || Floating Point Ceiling Convert to Word Fixed Point
|-
| {{mips|CVT.D.fmt}} || Floating Point Convert to Double Floating Point
|-
| {{mips|CVT.L.fmt}} || Floating Point Convert to Long Fixed Point
|-
| {{mips|CVT.PS.S}} || Floating Point Convert Pair to Paired Single
|-
| {{mips|CVT.S.PL}} || Floating Point Convert Pair Lower to Single Floating Point
|-
| {{mips|CVT.S.PU}} || Floating Point Convert Pair Upper to Single Floating Point
|-
| {{mips|CVT.S.fmt}} || Floating Point Convert to Single Floating Point
|-
| {{mips|CVT.W.fmt}} || Floating Point Convert to Word Fixed Point
|-
| {{mips|FLOOR.L.fmt}} || Floating Point Floor Convert to Long Fixed Point
|-
| {{mips|FLOOR.W.fmt}} || Floating Point Floor Convert to Word Fixed Point
|-
| {{mips|PLL.PS}} || Pair Lower Lower
|-
| {{mips|PLU.PS}} || Pair Lower Upper
|-
| {{mips|PUL.PS}} || Pair Upper Lower
|-
| {{mips|PUU.PS}} || Pair Upper Upper
|-
| {{mips|ROUND.L.fmt}} || Floating Point Round to Long Fixed Point
|-
| {{mips|ROUND.W.fmt}} || Floating Point Round to Word Fixed Point
|-
| {{mips|TRUNC.L.fmt}} || Floating Point Truncate to Long Fixed Point
|-
| {{mips|TRUNC.W.fmt}} || Floating Point Truncate to Word Fixed Point
|}


=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|LDC1}} || Load Doubleword to Floating Point
|-
| {{mips|LDXC1}} || Load Doubleword Indexed to Floating Point
|-
| {{mips|LUXC1}} || Load Doubleword Indexed Unaligned to Floating Point
|-
| {{mips|LWC1}} || Load Word to Floating Point
|-
| {{mips|LWXC1}} || Load Word Indexed to Floating Point
|-
| {{mips|PREFX}} || Prefetch Indexed
|-
| {{mips|SDC1}} || Store Doubleword from Floating Point
|-
| {{mips|SDXC1}} || Store Doubleword Indexed from Floating Point
|-
| {{mips|SUXC1}} || Store Doubleword Indexed Unaligned from Floating Point
|-
| {{mips|SWC1}} || Store Word from Floating Point
|-
| {{mips|SWXC1}} || Store Word Indexed from Floating Point
|}


=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|CFC1}} || Move Control Word from Floating Point
|-
| {{mips|CTC1}} || Move Control Word to Floating Point
|-
| {{mips|MFC1}} || Move Word from Floating Point
|-
| {{mips|MFHC1}} || Move Word from High Half of Floating Point Register
|-
| {{mips|MOV.fmt}} || Floating Point Move
|-
| {{mips|MOVF.fmt}} || Floating Point Move Conditional on Floating Point False
|-
| {{mips|MOVN.fmt}} || Floating Point Move Conditional on Not Zero
|-
| {{mips|MOVT.fmt}} || Floating Point Move Conditional on Floating Point True
|-
| {{mips|MOVZ.fmt}} || Floating Point Move Conditional on Zero
|-
| {{mips|MTC1}} || Move Word to Floating Point
|-
| {{mips|MTHC1}} || Move Word to High Half of Floating Point Register
|}

== Coprocessor instructions ==

=== Branch instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|BC2F}} || Branch on COP2 False
|-
| {{mips|BC2T}} || Branch on COP2 True
|-
| <strike>{{mips|BC2FL}}</strike> || Branch on COP2 False Likely
|-
| <strike>{{mips|BC2TL}}</strike> || Branch on COP2 True Likely
|}


=== Execute instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|COP2}} || Coprocessor Operation to Coprocessor 2
|}

=== Memory control instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|DC2}} || Load Doubleword to Coprocessor 2
|-
| {{mips|LWC2}} || Load Word to Coprocessor 2
|-
| {{mips|SDC2}} || Store Doubleword from Coprocessor 2
|-
| {{mips|SWC2}} || Store Word from Coprocessor 2
|}


=== Move instructions ===
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|CFC2}} || Move Control Word from Coprocessor 2
|-
| {{mips|CTC2}} || Move Control Word to Coprocessor 2
|-
| {{mips|MFC2}} || Move Word from Coprocessor 2
|-
| {{mips|MFHC2}} || Move Word from High Half of Coprocessor 2 Register
|-
| {{mips|MTC2}} || Move Word to Coprocessor 2
|-
| {{mips|MTHC2}} || Move Word to High Half of Coprocessor 2 Register
|}


== Privileged instructions ==
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|CACHE}} || Perform Cache Operation
|-
| {{mips|CACHEE}} || Perform Cache Operation EVA
|-
| {{mips|DI}} || Disable Interrupts
|-
| {{mips|EI}} || Enable Interrupts
|-
| {{mips|ERET}} || Exception Return
|-
| {{mips|MFC0}} || Move from {{mips|Coprocessor 0}}
|-
| {{mips|MTC0}} || Move to {{mips|Coprocessor 0}}
|-
| {{mips|RDPGPR}} || Read GPR from Previous Shadow Set
|-
| {{mips|TLBP}} || Probe TLB for Matching Entry
|-
| {{mips|TLBR}} || Read Indexed TLB Entry
|-
| {{mips|TLBWI}} || Write Indexed TLB Entry
|-
| {{mips|TLBWR}} || Write Random TLB Entry
|-
| {{mips|WAIT}} || Enter Standby Mode
|-
| {{mips|WRPGPR}} || Write GPR to Previous Shadow Set
|}

== EJTAG instructions ==
{| class="wikitable sortable"
! Mnemonic || Description
|-
| {{mips|DERET}} ||Debug Exception Return
|-
| {{mips|SDBBP}} || Software Debug Breakpoint
|}

== References ==
{{reflist|30em}}

[[Category:Assembly language]]
[[Category:MIPS]]
[[Category:MIPS32]]
[[Category:RISC instruction set]]
[[Category:Instruction set architecture]]