Semiconductor & Computer Engineering
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| − | {{title|Majority | + | {{title|Majority (MAJ) Gate}}{{logic device |
|title = MAJ Gate | |title = MAJ Gate | ||
|symbol title = Typical Symbol | |symbol title = Typical Symbol | ||
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The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]]. | The '''majority gate''' ('''MAJ gate''') is a [[logic gate]] that implements the [[majority function]] - a device that outputs a [[HIGH]] when the majority of its inputs are HIGH, otherwise it outputs a [[LOW]]. | ||
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== MAJ3 == | == MAJ3 == | ||
| − | [[File:MAJ3 gate.svg | + | <span style="display:inline-block;float: right; margin: 5px;">[[File:MAJ3 gate.svg|250px]]</span> |
| − | + | A 3-input MAJ gate (MAJ3) can be implemented as <math>(a \land b) \lor (a \land c) \lor (b \land c)</math>. However the naive implementation will result in up to 30 transistors. Since <math>\text{MAJ}(a, b, c) = \overline{\overline{\text{MAJ}(a, b, c)}}</math>, we can define <math>\text{MAJ}(a, b, c) = \overline{\overline{(a \land b) \lor (a \land c) \lor (b \land c)}}</math> and that can be implemented using a single [[AOI|AOI222]] which is defined as <math>\text{AOI222}(a, b, c, d, e, f) = \overline{(a \land b) \lor (c \land d) \lor (e \land f)}</math> - i.e. <math>\text{MAJ}(a, b, c) = \overline{AOI222(a, b, c, a, b, c)}</math>. | |
| − | A 3-input MAJ gate (MAJ3) can be implemented as <math>(a \land b) \lor (a \land c) \lor (b \land c)</math>. | ||
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| − | However the naive implementation will result in up to 30 transistors. Since | ||
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| − | and that can be implemented using a single [[ | ||
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