From WikiChip
Editing intel
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 20: | Line 20: | ||
In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | In addition to [[x86]], Intel used to also design and manufacture [[ARM]]-based chips as well as embed [[ARC]]-based cores in their products. While they no longer sell such chips, they still use ARM processors in various products (e.g. in their FPGAs) as well as still retain full a architectural level ARM license allowing them to design and sell their own ARM devices should they wish to. | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== Find Chip == | == Find Chip == | ||
Line 111: | Line 105: | ||
}} | }} | ||
− | == List of architectures == | + | == List of instruction set architectures == |
{{collist | {{collist | ||
| count = 1 | | count = 1 | ||
| | | | ||
− | * {{ | + | * {{intel|MCS-8/ISA|MCS-8 (8008)}} |
* [[x86]] | * [[x86]] | ||
− | * {{ | + | * {{intel|configurable spatial accelerator}} (CSA) |
− | |||
}} | }} | ||
Line 135: | Line 128: | ||
* {{intel|Enhanced NetBurst|l=arch}} | * {{intel|Enhanced NetBurst|l=arch}} | ||
}} | }} | ||
− | |||
{{collist | {{collist | ||
Line 141: | Line 133: | ||
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
− | '''Client | + | '''Client:''' |
* {{intel|Core (client)|l=arch}} | * {{intel|Core (client)|l=arch}} | ||
* {{intel|Penryn (client)|l=arch}} | * {{intel|Penryn (client)|l=arch}} | ||
Line 156: | Line 148: | ||
* {{intel|Amber Lake|l=arch}} | * {{intel|Amber Lake|l=arch}} | ||
* {{intel|Comet Lake|l=arch}} | * {{intel|Comet Lake|l=arch}} | ||
− | |||
− | |||
* {{intel|Cannon Lake|l=arch}} ("Skymont") | * {{intel|Cannon Lake|l=arch}} ("Skymont") | ||
* {{intel|Ice Lake (client)|l=arch}} | * {{intel|Ice Lake (client)|l=arch}} | ||
* {{intel|Tiger Lake|l=arch}} | * {{intel|Tiger Lake|l=arch}} | ||
* {{intel|Alder Lake|l=arch}} | * {{intel|Alder Lake|l=arch}} | ||
− | |||
* {{intel|Meteor Lake|l=arch}} | * {{intel|Meteor Lake|l=arch}} | ||
− | |||
− | |||
− | |||
}} | }} | ||
− | |||
{{collist | {{collist | ||
Line 174: | Line 159: | ||
| style= margin-left: 20px; | | style= margin-left: 20px; | ||
| | | | ||
− | '''Server | + | '''Server:''' |
* {{intel|Core (server)|l=arch}} | * {{intel|Core (server)|l=arch}} | ||
* {{intel|Penryn (server)|l=arch}} | * {{intel|Penryn (server)|l=arch}} | ||
Line 188: | Line 173: | ||
* {{intel|Ice Lake (server)|l=arch}} | * {{intel|Ice Lake (server)|l=arch}} | ||
* {{intel|Sapphire Rapids|l=arch}} | * {{intel|Sapphire Rapids|l=arch}} | ||
− | |||
* {{intel|Granite Rapids|l=arch}} | * {{intel|Granite Rapids|l=arch}} | ||
− | |||
}} | }} | ||
− | + | '''ULP ([[x86]]):''' | |
{{collist | {{collist | ||
− | | count = | + | | count = 2 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
| | | | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
* {{intel|Bonnell|l=arch}} | * {{intel|Bonnell|l=arch}} | ||
* {{intel|Saltwell|l=arch}} | * {{intel|Saltwell|l=arch}} | ||
Line 230: | Line 188: | ||
* {{intel|Tremont|l=arch}} | * {{intel|Tremont|l=arch}} | ||
}} | }} | ||
− | |||
'''MCU:''' | '''MCU:''' | ||
{{collist | {{collist | ||
Line 237: | Line 194: | ||
* {{intel|Lakemont|l=arch}} | * {{intel|Lakemont|l=arch}} | ||
}} | }} | ||
− | |||
'''ULP ([[ARM]]):''' | '''ULP ([[ARM]]):''' | ||
{{collist | {{collist | ||
Line 249: | Line 205: | ||
* Continued by [[Marvell]] .. | * Continued by [[Marvell]] .. | ||
}} | }} | ||
− | |||
− | |||
'''Server (EPIC) ([[Itanium]]):''' | '''Server (EPIC) ([[Itanium]]):''' | ||
{{collist | {{collist | ||
Line 299: | Line 253: | ||
| | | | ||
* {{intel|Lakefield|l=arch}} | * {{intel|Lakefield|l=arch}} | ||
− | |||
}} | }} | ||
Line 334: | Line 287: | ||
* {{intel|Arctic Sound|l=arch}} | * {{intel|Arctic Sound|l=arch}} | ||
* {{intel|Jupiter Sound|l=arch}} | * {{intel|Jupiter Sound|l=arch}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
Line 360: | Line 295: | ||
'''Neuromorphic:''' | '''Neuromorphic:''' | ||
* {{intel|Loihi}} | * {{intel|Loihi}} | ||
− | |||
'''Artificial Intelligence''' | '''Artificial Intelligence''' | ||
* {{intel|ETANN}} | * {{intel|ETANN}} | ||
Line 411: | Line 345: | ||
* {{\\|Dynamic Tuning}} | * {{\\|Dynamic Tuning}} | ||
* {{\\|Hyper Scaling}} | * {{\\|Hyper Scaling}} | ||
− | |||
* {{\\|Turbo Boost Technology}} (TBT) | * {{\\|Turbo Boost Technology}} (TBT) | ||
* {{\\|Thermal Velocity Boost}} (TVB) | * {{\\|Thermal Velocity Boost}} (TVB) | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
}} | }} | ||
Facts about "Intel"
company type | public + |
founded | July 18, 1968 + |
founded location | Mountain View, California + |
founder | Gordon Moore +, Robert Noyce + and Andrew Grove + |
full page name | intel + |
headquarters | Santa Clara, California + |
instance of | semiconductor company + |
name | Intel + |
website | http://www.intel.com + |
wikidata id | Q248 + |