From WikiChip
Editing intel/process-architecture-optimization
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
− | {{intel title| | + | {{intel title|P2 (PAO)}} |
− | '''[[name::Process-Architecture-Optimization]]''' | + | '''[[name::Process-Architecture-Optimization]]''' is a [[instance of::development model]] introduced by [[Intel]] for their mainstream microprocessors in [[2016]] following the phase-out of their {{intel|Tick-Tock}} model. The change is a result of the increase in cost and complexity of advancing lithography processes in the past decade. Under the new model the amount of time utilized for any given process technology is lengthen. |
Under the Process-Architecture-Optimization Model: | Under the Process-Architecture-Optimization Model: | ||
− | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently | + | * '''Process''' - With each process, Intel advances their manufacturing [[process technology]] in line with [[Moore's Law]]. Each new process introduces higher transistor density and a generally a plethora of other advantages such as higher performance and lower power consumption. During a "process", Intel retrofits their {{intel|microarchitectures|previous}} [[microarchitecture]] to the new process which inherently yielded better performance and energy saving. During a "process", usually just a few features and improvements and new instructions are introduced. |
− | * '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New | + | * '''Architecture''' - With each architecture, Intel uses the their latest manufacturing [[process technology]] from their "process" to manufacture a newly designed [[microarchitecture]]. The new microarchitecture is designed with the new process in mind and typically introduces Intel's newest big features and functionalities. New instructions are often added during this cycle stage. |
− | * '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. | + | * '''Optimization''' - With each optimization, Intel improves upon their {{intel|microarchitectures|previous}} microarchitecture by introducing incremental improvements and enhancements without introducing any large charges. Additional the process itself enjoys various refinements it matures. |
− | == | + | == Schedule == |
− | |||
{| class="wikitable" | {| class="wikitable" | ||
− | ! colspan="4" style="background:#D6D6FF;" | Intel | + | ! colspan="4" style="background:#D6D6FF;" | Intel Tick-Tock Schedule |
|- | |- | ||
!Cycle !! [[technology node|Process]] !! Introduction !! Microarchitecture | !Cycle !! [[technology node|Process]] !! Introduction !! Microarchitecture | ||
|- | |- | ||
− | | Process || [[14 nm]] || 2014 || {{intel|Broadwell| | + | | Process || [[14 nm]] || 2014 || {{intel|microarchitectures/Broadwell|Broadwell}} |
|- | |- | ||
− | | Architecture || [[14 nm]] || 2015 || {{intel|Skylake | + | | Architecture || [[14 nm]] || 2015 || {{intel|microarchitectures/Skylake|Skylake}} |
|- | |- | ||
− | | Optimization || [[14 nm | + | | Optimization || [[14 nm]] || 2016 || {{intel|microarchitectures/Kaby Lake|Kaby Lake}} |
|- | |- | ||
− | | Optimization || [[14 nm | + | | Optimization || [[14 nm]] || 2017 || {{intel|microarchitectures/Coffee Lake|Coffee Lake}} |
|- | |- | ||
− | | | + | | Process || [[10 nm]] || 2017 || {{intel|microarchitectures/Cannonlake|Cannonlake}} |
|- | |- | ||
− | | | + | | Architecture || [[10 nm]] || 2018 || {{intel|microarchitectures/Icelake|Icelake}} |
|- | |- | ||
− | | Optimization || [[ | + | | Optimization || [[10 nm]] || 2019 || {{intel|microarchitectures/Tigerlake|Tigerlake}} |
− | |||
− | |||
|} | |} | ||
− | |||
− |
Facts about "Process-Architecture-Optimization (PAO) - Intel"
instance of | development model + |
name | Process-Architecture-Optimization + |