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|speculative=Yes | |speculative=Yes | ||
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|isa=x86-64 | |isa=x86-64 | ||
|extension=MMX | |extension=MMX | ||
|extension 2=AVX | |extension 2=AVX | ||
|extension 3=AVX2 | |extension 3=AVX2 | ||
− | |extension 4=AVX-512 (needs | + | |extension 4=AVX-512 (needs Bios support and No E core) |
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! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! {{intel|Turbo Boost Max|TBMT}} | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! {{intel|Turbo Boost Max|TBMT}} | ||
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− | + | | [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || style="text-align: left;" | Mid-range Performance || [[10 cores|10]] (6+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} | |
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− | | [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || style="text-align: left;" | Mid-range Performance || [[10 cores|10]] (6+4 | ||
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| [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | High-end Performance || [[12 cores|12]] (8+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} | | [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | High-end Performance || [[12 cores|12]] (8+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} | ||
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Alder Lake | + | | rowspan="2" | {{intel|Alder Lake P|P|l=core}} || 0 || 0x6 || 0x9 || 0x7 |
|- | |- | ||
| colspan="4" | Family 6 Model 151 | | colspan="4" | Family 6 Model 151 | ||
|- | |- | ||
− | | rowspan="2" | {{intel|Alder Lake | + | | rowspan="2" | {{intel|Alder Lake S|S|l=core}} || 0 || 0x6 || 0x9 || 0xA |
|- | |- | ||
| colspan="4" | Family 6 Model 154 | | colspan="4" | Family 6 Model 154 | ||
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=== Key changes from {{\\|Tiger Lake}}=== | === Key changes from {{\\|Tiger Lake}}=== | ||
* Core | * Core | ||
− | ** Hybrid Golden Cove ( | + | ** Hybrid Golden Cove (big core) & Gracemont (small core) microarchitecture |
− | ** | + | ** At least 20% IPC improvements |
− | |||
− | |||
− | |||
** Intel 7 node | ** Intel 7 node | ||
* Memory | * Memory | ||
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== Overview == | == Overview == | ||
− | Alder Lake departs from all prior Intel SoCs by featuring the company's first mainstream implementation of a single-ISA heterogeneous multi-core microarchitecture. While not the first ({{\\|Lakefield}} was), Alder Lake is the first to target all market segments from mobile to desktop and workstation. The overall microarchitecture builds on its predecessor, {{\\|Tigerlake}} but expends on its by integrating two vastly different types of cores - up to eight [[big cores]] based on the {{\\|Golden Cove}} microarchitecture and up to eight [[small cores]] based on the {{\\|Gracemont}} microarchitecture. The big cores are designed to push single-thread performance while the small cores are designed to push multi-thread power efficiency. By finely orchestrating thread scheduling based on performance demand, Alder Lake is able to provide both higher multi-threading performance-efficiency and better single-thread performance. | + | Alder Lake departs from all prior Intel SoCs by featuring the company's first mainstream implementation of a single-ISA heterogeneous multi-core microarchitecture. While not the first ({{\\|Lakefield}} was), Alder Lake is the first to target all market segments from mobile to desktop and workstation. The overall microarchitecture builds on its its predecessor, {{\\|Tigerlake}} but expends on its by integrating two vastly different types of cores - up to eight [[big cores]] based on the {{\\|Golden Cove}} microarchitecture and up to eight [[small cores]] based on the {{\\|Gracemont}} microarchitecture. The big cores are designed to push single-thread performance while the small cores are designed to push multi-thread power efficiency. By finely orchestrating thread scheduling based on performance demand, Alder Lake is able to provide both higher multi-threading performance-efficiency and better single-thread performance. |
=== SoC design === | === SoC design === | ||
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{| class="wikitable" | {| class="wikitable" | ||
− | ! colspan=" | + | ! colspan="4" | Die |
|- | |- | ||
− | ! Name !! | + | ! Name !! Configuration !! Dimensions !! Area |
|- | |- | ||
− | | rowspan="2" | ADL-S || 8P + 8E | + | | rowspan="2" | ADL-S || 8P + 8E || 10.5 mm x 20.5 mm || 215.25 mm² |
|- | |- | ||
| 6P + 0E || 10.5 mm x 15.5 mm || 162.75 mm² | | 6P + 0E || 10.5 mm x 15.5 mm || 162.75 mm² | ||
|- | |- | ||
− | | ADL-P || 6P + 8E | + | | ADL-P || 6P + 8E |
|- | |- | ||
| ADL-M || 2P + 8E | | ADL-M || 2P + 8E | ||
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=== ADL-S (8P+8E) === | === ADL-S (8P+8E) === | ||
* 8 performance cores + 8 efficiency cores | * 8 performance cores + 8 efficiency cores | ||
− | |||
* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 20.5 mm | * 10.5 mm x 20.5 mm | ||
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=== ADL-S (6P+0E) === | === ADL-S (6P+0E) === | ||
* 6 performance cores, no efficiency cores | * 6 performance cores, no efficiency cores | ||
− | |||
* [[Intel 7]] process | * [[Intel 7]] process | ||
* 10.5 mm x 15.5 mm | * 10.5 mm x 15.5 mm |
Facts about "Alder Lake - Microarchitectures - Intel"
codename | Alder Lake + |
designer | Intel + |
first launched | 2021 + |
full page name | intel/microarchitectures/alder lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Alder Lake + |
processing element count | 32 EU igpu + and 96 EU igpu + |