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| | |manufacturer=Intel | | |manufacturer=Intel |
| | |introduction=2021 | | |introduction=2021 |
| − | |process=intel 7 (10nm ESF) | + | |process=10 nm |
| − | |cores=8P+8E
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| − | |cores 2=6P+8E
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| − | |cores 3=6P+0E
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| − | |cores 4=2P+8E
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| − | |processing elements=32 EU igpu
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| − | |processing elements 2=96 EU igpu
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| − | |oooe=Yes
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| − | |speculative=Yes
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| − | |renaming=Yes
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| | |isa=x86-64 | | |isa=x86-64 |
| − | |extension=MMX
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| − | |extension 2=AVX
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| − | |extension 3=AVX2
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| − | |extension 4=AVX-512 (needs BIOS support and no E core)
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| − | |l1i=32 KB
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| − | |l1i per=core
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| − | |l1d=48 KB (P) / 64 KB (E)
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| − | |l1d per=core
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| − | |l1=80 KB (P) / 96 KB (E)
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| − | |l1 per=core
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| − | |l2=1.25 MB (P) / 2MB (4E)
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| − | |l2 per=core
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| − | |l3=up to 30 MB
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| − | |core name=[[::intel/microarchitectures/golden_cove|Golden Cove]]
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| − | |core name 2=[[::intel/microarchitectures/gracemont|Gracemont]]
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| | |predecessor=Tiger Lake | | |predecessor=Tiger Lake |
| | |predecessor link=intel/microarchitectures/tiger lake | | |predecessor link=intel/microarchitectures/tiger lake |
| | |predecessor 2=Rocket Lake | | |predecessor 2=Rocket Lake |
| | |predecessor 2 link=intel/microarchitectures/rocket lake | | |predecessor 2 link=intel/microarchitectures/rocket lake |
| − | |predecessor 3=Lakefield
| + | |successor=Meteor Lake |
| − | |predecessor 3 link=intel/microarchitectures/lakefield
| + | |successor link=intel/microarchitectures/meteor lake |
| − | |successor=Raptor Lake
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| − | |successor link=intel/microarchitectures/raptor lake
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| − | |successor 2=Meteor Lake | |
| − | |successor 2 link=intel/microarchitectures/meteor lake | |
| | }} | | }} |
| − | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to both {{\\|Tiger Lake}} and {{\\|Rocket Lake}}, an [[Intel 7]]-process based [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. Alder Lake is Intel's first [[10-nanometer]]-class proper successor to all prior generation of processors - spanning from ultra-low power to desktop and workstations. The microarchitecture was developed by Intel's R&D center in [[wikipedia:Haifa, Israel|Haifa, Israel]]. | + | '''Alder Lake''' ('''ADL''') is [[Intel]]'s successor to {{\\|Tiger Lake}}, a [[10 nm]] [[microarchitecture]] for mainstream workstations, desktops, and mobile devices. |
| | | | |
| − | For desktop and mobile, Alder Lake is branded as 12th Generation Intel {{intel|Core i3}}, {{intel|Core i5}}, {{intel|Core i7}}, and {{intel|Core i9}} processors.
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| − |
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| − | == Codenames ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Core !! Abbrev !! Platform !! Target
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| − | |-
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| − | | {{intel|Alder Lake M|l=core}} || ADL-M || || Light notebooks, 2-in-1s detachable, tablets, conference room, computer sticks, etc.
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| − | |-
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| − | | {{intel|Alder Lake P|l=core}} || ADL-P || || Ultimate mobile performance, mobile workstations, portable All-in-Ones (AiOs), Minis
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| − | |-
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| − | | {{intel|Alder Lake S|l=core}} || ADL-S || || Desktop performance to value, AiOs, and minis
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| − | |}
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| − |
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| − | == Brands ==
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| − | Intel released Alder Lake under 3 main brand families for mainstream workstations, desktops, and mobile.
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| − |
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| − | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
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| − | |-
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| − | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="7" | Differentiating Features
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| − | |-
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| − | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! {{intel|Turbo Boost Max|TBMT}}
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| − | |-
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| − | | [[File:core i3 logo (2020).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || style="text-align: left;" | Low-end Performance || [[4 cores|4]] (4+0) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| − | |-
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| − | | [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || style="text-align: left;" | Mid-range Performance || [[10 cores|10]] (6+4)<br> [[6 cores|6]] (6+0) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| − | |-
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| − | | [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || style="text-align: left;" | High-end Performance || [[12 cores|12]] (8+4) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
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| − | |-
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| − | | [[File:core i9 logo (2020).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || style="text-align: left;" | Extreme Performance || [[16 cores|16]] (8+8) || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}}
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| − | |}
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| | | | |
| | + | {{future information}} |
| | == Process Technology== | | == Process Technology== |
| − | Intel is planning Alder Lake to be built on an improved Intel 7 node (previously 10nm Enhanced SuperFin (ESF)). This will be the case for both the powerful Golden Cove cores, and Gracemont cores.
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| − |
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| − | == Compiler support ==
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| − | {| class="wikitable"
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| − | |-
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| − | ! Compiler !! Arch-Specific || Arch-Favorable
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| − | |-
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| − | | [[ICC]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
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| − | |-
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| − | | [[GCC]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
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| − | |-
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| − | | [[LLVM]] || <code>-march=alderlake</code> || <code>-mtune=alderlake</code>
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| − | |-
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| − | | [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/tune:alderlake</code>
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| − | |}
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| − |
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| − | === CPUID ===
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| − | {| class="wikitable tc1 tc2 tc3 tc4"
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| − | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model
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| − | |-
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| − | | rowspan="2" | {{intel|Alder Lake S|S|l=core}} || 0 || 0x6 || 0x9 || 0x7
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| − | |-
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| − | | colspan="4" | Family 6 Model 151
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| − | |-
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| − | | rowspan="2" | {{intel|Alder Lake P|P|l=core}} || 0 || 0x6 || 0x9 || 0xA
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| − | |-
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| − | | colspan="4" | Family 6 Model 154
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| − | |}
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| | | | |
| | == History == | | == History == |
| − | In January 2021 Intel teased Alder Lake in their CES 2021 speech. On the July 26th's Intel Accelerated webcast, CEO Pat Gelsinger hinted at the Alder Lake lineup being released at a future event called "Intel Innovation" which aired between October 27-28th.
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| | | | |
| | == Architecture == | | == Architecture == |
| | + | |
| | | | |
| | === Key changes from {{\\|Tiger Lake}}=== | | === Key changes from {{\\|Tiger Lake}}=== |
| | * Core | | * Core |
| − | ** Hybrid Golden Cove (performance core) & Gracemont (efficiency core) microarchitecture | + | ** Hybrid Golden Cove(big core) & Gracemont(small core) microarchitecture |
| − | ** Higher IPC(Intel self-reported 19% IPC)
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| − | *** Some common integer ALU ops (CMP,TEST,AND,OR,XOR,LEA) increased throughput by 1 insn/cycle
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| − | *** Vector floating point addition/subtraction latency decreased from 4 to 2 cycles
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| − | *** [V]PCLMULQDQ latency decreased from 8/6 to 3 cycles
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| − | ** Intel 7 node
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| − | * Memory
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| − | ** Support for DDR5
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| − | ** Speeds of at least 4800MHz, up to 5600MHz
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| − | * Improved power delivery system
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| − | | |
| − | == Overview ==
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| − | Alder Lake departs from all prior Intel SoCs by featuring the company's first mainstream implementation of a single-ISA heterogeneous multi-core microarchitecture. While not the first ({{\\|Lakefield}} was), Alder Lake is the first to target all market segments from mobile to desktop and workstation. The overall microarchitecture builds on its predecessor, {{\\|Tigerlake}} but expends on its by integrating two vastly different types of cores - up to eight [[big cores]] based on the {{\\|Golden Cove}} microarchitecture and up to eight [[small cores]] based on the {{\\|Gracemont}} microarchitecture. The big cores are designed to push single-thread performance while the small cores are designed to push multi-thread power efficiency. By finely orchestrating thread scheduling based on performance demand, Alder Lake is able to provide both higher multi-threading performance-efficiency and better single-thread performance.
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| − | | |
| − | === SoC design ===
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| − | {{empty section}}
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| − | | |
| − | == Die ==
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| − | Alder Lake comes in four die variants depending on the market segment.
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| − | | |
| − | {| class="wikitable"
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| − | ! colspan="5" | Die
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| − | |-
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| − | ! Name !! CPU Configuration !! GPU !! Dimensions !! Area
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| − | |-
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| − | | rowspan="2" | ADL-S || 8P + 8E || rowspan="2" | 32 EU || 10.5 mm x 20.5 mm || 215.25 mm²
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| − | |-
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| − | | 6P + 0E || 10.5 mm x 15.5 mm || 162.75 mm²
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| − | |-
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| − | | ADL-P || 6P + 8E || rowspan="2" | 96 EU
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| − | |-
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| − | | ADL-M || 2P + 8E
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| − | |}
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| − | | |
| − | === ADL-S (8P+8E) ===
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| − | * 8 performance cores + 8 efficiency cores
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| − | * 32 EU gpu (256 shaders)
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| − | * [[Intel 7]] process
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| − | * 10.5 mm x 20.5 mm
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| − | ** 215.25 mm² die size
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| − | | |
| − | | |
| − | :[[File:alder lake die 2.png|900px]]
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| − | | |
| − | | |
| − | :[[File:alder lake die.png|850px]]
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| − | | |
| − | === ADL-S (6P+0E) ===
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| − | * 6 performance cores, no efficiency cores
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| − | * 32 EU gpu (256 shaders)
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| − | * [[Intel 7]] process
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| − | * 10.5 mm x 15.5 mm
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| − | ** 162.75 mm² die size
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| − | | |
| − | === Additional Shots ===
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| − | [[File:alder lake partial wafer shot.jpg|850px]]
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