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{{fairchild title|4700 Series}}
 
{{fairchild title|4700 Series}}
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{{ic family
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The '''Fairchild 4700 Series''' is a [[microprocessor family|family]] of [[4-bit architecture|4-bit]] [[CMOS]] [[bit-slice microprocessor|bit-slice]] chips designed by [[Fairchild Semiconductor]]. The series was introduced in 1975{{date off}}.
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| title            = Fairchild 4700 Family
 
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| image            = <!-- Image representation of the IC family, e.g. "MCS-4.jpg"  -->
 
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| caption          = <!-- description of the image                                  -->
 
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| developer        = Fairchild Semiconductor
 
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| manufacturer      = Fairchild Semiconductor
 
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| type              = microprocessors
 
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| production start  = 1975
 
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| production end    = <!-- production end date, e.g. "January 1, 1985" or "1973"    -->
 
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| arch              = 4-bit bit-slice
 
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| word              = 4 bit
 
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| proc              = <!-- process, e.g. "8 μm"                                      -->
 
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| tech              = CMOS
 
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| clock            = 2.4576 MHz
 
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| package          = DIP24
 
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| package 2        = CerDIP24
 
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}}
 
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The '''4700 Series''' (officially '''4700 Macrologic Series CMOS Family''') was a [[microprocessor family|family]] of {{arch|4}} [[CMOS]] multi-chip [[bit-slice microprocessor]] designed by [[Fairchild Semiconductor]]. The series was introduced in 1975. Around the same time Fairchild introduced the {{fairchild|9400|9400 series}} which was a similar family using bipolar technology instead.
 
  
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== 2nd Source ==
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{| class="wikitable" style="float: right;"
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This family was 2nd sourced by [[Signetics]].
 
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== Members ==
 
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{| class="wikitable"
 
 
! colspan="2" | Family Members
 
! colspan="2" | Family Members
 
|-
 
|-
 
! Part !! Description
 
! Part !! Description
 
|-
 
|-
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| {{\|4702}} || Bit-rate generator
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| {{fairchild|4702}} || Bit-rate generator
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|-
 
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| {{\|4703}} || Series/Parallel [[FIFO]] (Buffer Memory)
 
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|-
 
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| {{\|4704}} || [[Data Path Switch]] (DPS)
 
 
|-
 
|-
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| {{\|4705}} || Microprocessor "ALRS" (Arithmetic Logic Register Stack)
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| {{fairchild|4703}} || Series/Parallel [[FIFO]] (Buffer Memory)
 
|-
 
|-
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| {{\|4706}} || Program Stack
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| {{fairchild|4704}} || [[Data Path Switch]] (DPS)
 
|-
 
|-
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| {{\|4707}} || Data Access Register
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| {{fairchild|4705}} || Microprocessor "ALRS" (Arithmetic Logic Register Stack)
 
|-
 
|-
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| {{\|4708}} || Microprogram Sequencer
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| {{fairchild|4706}} || Program Stack
 
|-
 
|-
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| {{\|4710}} || 16x4-bit RAM Register Stack
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| {{fairchild|4707}} || Data Access Register
 
|-
 
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| {{\|4720}} || 256x1-bit RAM Register Stack
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| {{fairchild|4708}} || Microprogram Sequencer
 
|-
 
|-
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| {{\|4726}} || 256x4-bit RAM Register Stack
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| {{fairchild|4710}} || 16x4-bit RAM Register Stack
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|-
 
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| {{\|4735}} || 256x8-bit RAM Register Stack
 
 
|}
 
|}
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== Architecture ==
 
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The individual chips were designed such that they may be chained in cascading manner to support any word size desired (usually multiples of 4). The operations themselves are spread throughout the family, for example 16 register manipulations were provided by the DAR ({{\|4707}}), 8 arithmetic by the ALRS ({{\|4705}}), and 30 shifting/masking/extending operation were provided by the DPS ({{\|4704}}).
 
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There is no actual ISA, it was up to the designer to develop one and assemble the chips accordingly.
 
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{{expand section}}
 
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== See also ==
 
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* {{fairchild|9400|Fairchild 9400 Family}}
 
  
  

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Facts about "4700 Series - Fairchild"
RDF feed
designerFairchild Semiconductor +
full page namefairchild/4700 +
instance ofmicroprocessor family +
main designerFairchild Semiconductor +
manufacturerFairchild Semiconductor +
nameFairchild 4700 Family +
packageDIP24 + and CerDIP24 +
technologyCMOS +
word size4 bit (0.5 octets, 1 nibbles) +