From WikiChip
Editing chip multiprocessor
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
− | {{title|Chip Multiprocessor | + | {{title|Chip Multiprocessor}} |
A '''chip multiprocessor''' ('''CMP''') or '''multi-core''' [[microprocessor architecture|architecture]] is a [[logic]] design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple [[dies]] in a single [[package]]. | A '''chip multiprocessor''' ('''CMP''') or '''multi-core''' [[microprocessor architecture|architecture]] is a [[logic]] design architecture whereby multiple processing units (e.g., CPU cores) are integrated onto a single monolithic integrated circuit or onto multiple [[dies]] in a single [[package]]. | ||
Line 9: | Line 9: | ||
=== Heterogeneous multi-core architectures === | === Heterogeneous multi-core architectures === | ||
− | {{empty section}} | + | {{empty section}} |
==== Single and Multi-ISA designs ==== | ==== Single and Multi-ISA designs ==== | ||
− | |||
− | |||
− | |||
− | |||
{{empty section}} | {{empty section}} | ||
== Multi-core chips == | == Multi-core chips == | ||
{{collist | {{collist | ||
− | | count = | + | | count = 4 |
| | | | ||
* {{\\|2|2 (dual-core)}} | * {{\\|2|2 (dual-core)}} | ||
Line 55: | Line 51: | ||
* {{\\|46|46 (hexatetraconta-core)}} | * {{\\|46|46 (hexatetraconta-core)}} | ||
* {{\\|48|48 (octatetraconta-core)}} | * {{\\|48|48 (octatetraconta-core)}} | ||
− | |||
* {{\\|64|64 (tetrahexaconta-core)}} | * {{\\|64|64 (tetrahexaconta-core)}} | ||
− | |||
* {{\\|128|128 (octacosahecta-core)}} | * {{\\|128|128 (octacosahecta-core)}} | ||
* {{\\|256|256 (hexapentacontadicta-core)}} | * {{\\|256|256 (hexapentacontadicta-core)}} | ||
Line 63: | Line 57: | ||
* {{\\|1000|1000 (kilo-core)}} | * {{\\|1000|1000 (kilo-core)}} | ||
* {{\\|1024|1024 (tetracosakilia-core)}} | * {{\\|1024|1024 (tetracosakilia-core)}} | ||
− | |||
}} | }} | ||
− | === Recent | + | === Recent multi-core chips === |
− | The following | + | The following are current multi-core chips: |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
== See also == | == See also == |