Editing cavium/octeon tx

{{cavium title|OCTEON TX}}
{{ic family
| title             = Cavium OCTEON TX
| no image          = Yes
| image             = 
| caption           = 
| developer         = Cavium
| manufacturer      = 
| type              = System on chips
| first announced   = May 2, 2016
| first launched    = 
| production start  = 
| production end    = 
| arch              = 
| isa               = ARMv8
| microarch         = ThunderX
| word              = 64 bit
| proc              = 
| tech              = CMOS
| clock min         = 
| clock max         = 2,200 MHz
| package           = 1676 BGA
| package 2         = 676 FCBGA
| package 3         = 555 FCBGA
| socket            = 
| socket 2          = 

| succession       = Yes
| predecessor      = OCTEON III
| predecessor link = cavium/octeon iii
| successor        = 
| successor link   = 
}}
'''OCTEON TX''' is a family of {{arch|64}} [[multi-core]] [[ARM]] microprocessors designed by [[Cavium]] and introduced in [[2016]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON TX family combines the features of the {{\\|OCTEON}} family with the technology of the ThunderX processors.

== Overview ==


== Members ==
=== CN80xx Series ===
The CN80xx series come with [[2 cores|2]] to [[4 cores|4]] {{cavium|thunderx1|l=arch}} cores. Running at 800-1500MHz.
=== CN81xx Series ===
The CN81xx series come with [[2 cores|2]] to [[4 cores|4]] {{cavium|thunderx1|l=arch}} cores.  Running at 1200-2000MHz.
=== CN82xx Series ===
The CN82xx series come with [[8 cores|8]] to [[12 cores|12]] {{cavium|thunderx1|l=arch}} cores.  Running at 1200-1800MHz.
=== CN83xx Series ===
The CN83xx series come with [[8 cores|8]] to [[24 cores|24]] {{cavium|thunderx1|l=arch}} cores.  Running at 1500-2200MHz.

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<div style="overflow-x: auto;">
<table class="wikitable sortable tc4 tc10 tc11 tc12 tc13 tc14 tc15" style="min-width: 1200px;">
<tr><th colspan="14" style="background:#D6D6FF;">CN83xx-Series Microprocessors</th></tr>
<tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="4">[[Hardware Accelerators]]</th></tr>
<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>TCP</th><th>QoS</th></tr>
{{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON TX]][[microprocessor series::CN83xx]]
 |?full page name
 |?model number
 |?release price
 |?first launched
 |?core count
 |?l2$ size#MiB
 |?power dissipation
 |?base frequency
 |?supported memory type
 |?max memory
 |?has ecc memory support
 |?has hardware accelerators for cryptography
 |?has hardware accelerators for data compression
 |?has hardware accelerators for tcp packet processing
 |?has hardware accelerators for network quality of service processing
 |format=template
 |template=proc table 3
 |userparam=15:11
 |mainlabel=-
 |sort=model number
}}
{{table count|col=14|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN83xx]]}}
</table>
</div>

== Datasheet ==
* [[https://www.marvell.com/documents/ob2v9t3r0eltazxb8lqb/|OCTEON TX CN80XX and CN81XX Product Brief]]
* [[https://www.marvell.com/documents/mynw29omw68i8xxsxu7h/|OCTEON TX CN82XX and CN83XX Product Brief]]
designer	Cavium +
first announced	May 2, 2016 +
full page name	cavium/octeon tx +
instance of	system on a chip family +
instruction set architecture	ARMv8 +
main designer	Cavium +
microarchitecture	ThunderX +
name	Cavium OCTEON TX +
package	1676 BGA +, 676 FCBGA + and 555 FCBGA +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +