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|manufacturer=TSMC | |manufacturer=TSMC | ||
|introduction=Oct 30, 2012 | |introduction=Oct 30, 2012 | ||
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|predecessor=Cortex-A15 | |predecessor=Cortex-A15 | ||
|predecessor link=arm_holdings/microarchitectures/cortex-a15 | |predecessor link=arm_holdings/microarchitectures/cortex-a15 | ||
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}} | }} | ||
'''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A57''' (codename '''Atlas''') is the successor to the {{armh|Cortex-A15|l=arch}}, a low-power high-performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A57, which implemented the {{arm|ARMv8}} ISA, is the a performant core which is often combined with a number of lower power cores (e.g. {{\\|Cortex-A53}}) in a {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
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== Architecture == | == Architecture == | ||
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== Die == | == Die == | ||
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=== 20 nm === | === 20 nm === | ||
==== Samsung [[Exynos 5433]] ==== | ==== Samsung [[Exynos 5433]] ==== | ||
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* 113 mm² die size | * 113 mm² die size | ||
* Mali-T760 (6 EU) | * Mali-T760 (6 EU) | ||
− | * Quad-core { | + | * Quad-core {{\\|Cortex-A53}} ([[small cores]]) |
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2 | ** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2 | ||
** 4.4 mm² per cluster | ** 4.4 mm² per cluster | ||
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** ~3.27 mm² cluster | ** ~3.27 mm² cluster | ||
** ~0.60 mm² core | ** ~0.60 mm² core | ||
− | ** ~0.7 mm² | + | ** ~0.7`mm² L2 cache |
* Quad-core Cortex-A57 | * Quad-core Cortex-A57 | ||
** ~10.21 mm² cluster | ** ~10.21 mm² cluster | ||
** ~1.66 mm² core | ** ~1.66 mm² core | ||
− | ** ~3.28 mm² | + | ** ~3.28 mm² L2 cache |
* {{\\|Cortex-R7}} (dual-core [[lock-step]]) | * {{\\|Cortex-R7}} (dual-core [[lock-step]]) | ||
** ~1.04 mm² cluster | ** ~1.04 mm² cluster | ||
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: [[File:r-car h3 die shot.png|650px]] | : [[File:r-car h3 die shot.png|650px]] | ||
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== Bibliography == | == Bibliography == | ||
* Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015 | * Pyo, Jungyul, et al. "23.1 20nm high-K metal-gate heterogeneous 64b quad-core CPUs and hexa-core GPU for high-performance and energy-efficient mobile application processor." Solid-State Circuits Conference-(ISSCC), 2015 IEEE International. IEEE, 2015 |
Facts about "Cortex-A57 - Microarchitectures - ARM"
codename | Cortex-A57 + |
designer | ARM Holdings + |
first launched | October 30, 2012 + |
full page name | arm holdings/microarchitectures/cortex-a57 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A57 + |