Editing arm holdings/microarchitectures/cortex-a34

{{armh title|Cortex-A34|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A34
|designer=ARM Holdings
|manufacturer=TSMC
|stages=8
|isa=ARMv8 AArch64
|extension=NEON (optional)
|extension 2=Cryptography (optional)
|l1i=8k-64k
|l1d=8k-64k
|l2=128KB-1MB
|predecessor=Cortex-A35
|predecessor link=arm_holdings/microarchitectures/cortex-a35
}}
'''Cortex-A34''' (codenamed '''Metis''') is the successor to the {{\\|Cortex-A35}}, an ultra-low power [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.

== Architecture ==

=== Key changes from {{\\|Cortex-A5}} ===
{{empty section}}

== Specifications ==
{| class="wikitable"
|-
| Architecture || 64-Bit Armv8-A (AArch64 only)
|-
| Pipeline || In order
|-
| L1 I-Cache / D-Cache || 8k-64k
|-
| L2 Cache || 128KB-1MB
|-
| Multicore || 1-4x Symmetrical Multiprocessing (SMP) within a single processor cluster, and multiple coherent SMP processor clusters through AMBA 4 technology
|-
| ISA Support || AArch64 for 64-bit support and new architectural features<br />TrustZone security technology<br />Neon Advanced SIMD<br />DSP and SIMD extensions<br />VFPv4 Floating point<br />Hardware virtualization support
|-
| Debug & Trace || CoreSight SoC-400
|}
codename	Cortex-A34 +
designer	ARM Holdings +
full page name	arm holdings/microarchitectures/cortex-a34 +
instance of	microarchitecture +
instruction set architecture	ARMv8 AArch64 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Cortex-A34 +
pipeline stages	8 +